JPS5893008U - FET oscillator - Google Patents

FET oscillator

Info

Publication number
JPS5893008U
JPS5893008U JP18837181U JP18837181U JPS5893008U JP S5893008 U JPS5893008 U JP S5893008U JP 18837181 U JP18837181 U JP 18837181U JP 18837181 U JP18837181 U JP 18837181U JP S5893008 U JPS5893008 U JP S5893008U
Authority
JP
Japan
Prior art keywords
fet
oscillator
power supply
fet oscillator
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18837181U
Other languages
Japanese (ja)
Inventor
好孜 町野
長瀬　勝照
智彦 小野
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP18837181U priority Critical patent/JPS5893008U/en
Publication of JPS5893008U publication Critical patent/JPS5893008U/en
Pending legal-status Critical Current

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来におけるドレイン接地形のＦＥＴ発振器の
回路図、第２図はこの考案の一実施例を示す回路図であ
り、図中、１はＦＥＴ、２はベート電圧設定用電源、３
はソース電圧設定用電源、４はドレイン端子、５はゲー
ト端子、６はソース端子、７，８は電流制限抵抗、９は
電源端子、１０はダイオード、１１．１２はゲート電圧
設定用抵抗である。なお、図中間であるいは相当部分に
は同一符号を付して示しである。Fig. 1 is a circuit diagram of a conventional FET oscillator with a grounded drain configuration, and Fig. 2 is a circuit diagram showing an embodiment of this invention.
is a source voltage setting power supply, 4 is a drain terminal, 5 is a gate terminal, 6 is a source terminal, 7 and 8 are current limiting resistors, 9 is a power supply terminal, 10 is a diode, and 11.12 are gate voltage setting resistors. . Note that the same reference numerals are given to the middle parts of the figures or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＦＥＴのドレイン端子を接地したＦＥＴ発振器において
、一つの電源の負側にＦＥＴのソース端子を抵抗を介し
て接続するとともに、上記ＦＥＴのゲート端子が、その
カソードが上記電源の負側とつながるダイオード、およ
びこのダイオードに直列接続した別の抵抗を介して接続
したことを特徴とするＦＥＴ発振器。In an FET oscillator in which the drain terminal of the FET is grounded, the source terminal of the FET is connected to the negative side of one power supply via a resistor, and the gate terminal of the FET is connected to a diode whose cathode is connected to the negative side of the power supply. and an FET oscillator, characterized in that it is connected to this diode via another resistor connected in series.
JP18837181U 1981-12-17 1981-12-17 FET oscillator Pending JPS5893008U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18837181U JPS5893008U (en) 1981-12-17 1981-12-17 FET oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18837181U JPS5893008U (en) 1981-12-17 1981-12-17 FET oscillator

Publications (1)

Publication Number Publication Date
JPS5893008U true JPS5893008U (en) 1983-06-23

Family

ID=29991889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18837181U Pending JPS5893008U (en) 1981-12-17 1981-12-17 FET oscillator

Country Status (1)

Country Link
JP (1) JPS5893008U (en)

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