JPS6025221U

JPS6025221U - bias circuit

Info

Publication number: JPS6025221U
Application number: JP11571683U
Authority: JP
Inventors: 景一加藤; 省三郎亀田
Original assignee: 日本電気株式会社
Priority date: 1983-07-26
Filing date: 1983-07-26
Publication date: 1985-02-20

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のバイアス回路の回路図、第２図、第３図
、第４図は本考案の第１、第２、第３の実施例の回路図
である。図において、１、２．　３．４．　８．３０．
３１・・・・・・抵抗器、５．６・・・・・・定電圧源
、７・・・・・・ＦＥＴ、　９・・・・・・定電圧ダイ
オード、１０・・・・・・切換器、１１，１２，１３．
１６・・・・・・接触端子、１４・・・・・・中継端子
、１５・・・・・・接触子、２１・・・・・・ゲート端
子、２２・・・・・・ドレイン端子、２３・・・・・・
ソース端子、である。FIG. 1 is a circuit diagram of a conventional bias circuit, and FIGS. 2, 3, and 4 are circuit diagrams of first, second, and third embodiments of the present invention. In the figure, 1, 2. 3.4. 8.30.
31... Resistor, 5.6... Constant voltage source, 7... FET, 9... Constant voltage diode, 10... Switch, 11, 12, 13.
16... Contact terminal, 14... Relay terminal, 15... Contact, 21... Gate terminal, 22... Drain terminal, 23...
This is the source terminal.

Claims

[Scope of utility model registration request]

A voltage divider circuit that divides the voltage of a bias power supply using a plurality of resistors connected in series, a switch to which a switching terminal is connected to the connection point of each resistor of the voltage divider circuit, and a switch connected to the gate of the FET. A bias circuit comprising: a bias resistor connected between a common terminal of a switch and a predetermined bias voltage or ground, and configured to prevent a large current from flowing through the FET when the switch is switched.