JPS62143320U - - Google Patents

Info

Publication number
JPS62143320U
JPS62143320U JP3036286U JP3036286U JPS62143320U JP S62143320 U JPS62143320 U JP S62143320U JP 3036286 U JP3036286 U JP 3036286U JP 3036286 U JP3036286 U JP 3036286U JP S62143320 U JPS62143320 U JP S62143320U
Authority
JP
Japan
Prior art keywords
resistance section
variable
bias circuit
section
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3036286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3036286U priority Critical patent/JPS62143320U/ja
Publication of JPS62143320U publication Critical patent/JPS62143320U/ja
Pending legal-status Critical Current

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  • Microwave Amplifiers (AREA)
  • Amplifiers (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案のバイアス回路の一実施例を
示す図、第2図はこの考案によるバイアス回路を
セラミツク基板上に形成した実施例を示す図、第
3図は従来のバイアス回路を示す図である。図に
おいて、1は可変用抵抗、2は固定抵抗、3はジ
ヤンパ線、4はFET増幅器、5はパターン、6
はセラミツク基板、7は従来の可変抵抗器である
。なお、図中、同一符号は同一、又は相当部分を
示す。
Fig. 1 shows an embodiment of the bias circuit of this invention, Fig. 2 shows an embodiment of the bias circuit of this invention formed on a ceramic substrate, and Fig. 3 shows a conventional bias circuit. It is. In the figure, 1 is a variable resistor, 2 is a fixed resistor, 3 is a jumper wire, 4 is a FET amplifier, 5 is a pattern, and 6
is a ceramic substrate, and 7 is a conventional variable resistor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧分圧用可変抵抗器を有し、その抵抗部を可
変用抵抗部と固定抵抗部に分け、更に可変抵抗部
抵抗値をデイジタル的にかつ機械的に可変可能と
したことを特徴とするバイアス回路。
A bias circuit characterized in that it has a variable resistor for voltage division, its resistance section is divided into a variable resistance section and a fixed resistance section, and the resistance value of the variable resistance section can be varied digitally and mechanically. .
JP3036286U 1986-03-03 1986-03-03 Pending JPS62143320U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3036286U JPS62143320U (en) 1986-03-03 1986-03-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3036286U JPS62143320U (en) 1986-03-03 1986-03-03

Publications (1)

Publication Number Publication Date
JPS62143320U true JPS62143320U (en) 1987-09-10

Family

ID=30835094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3036286U Pending JPS62143320U (en) 1986-03-03 1986-03-03

Country Status (1)

Country Link
JP (1) JPS62143320U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0583041A (en) * 1990-11-30 1993-04-02 Nec Corp Gate bias control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0583041A (en) * 1990-11-30 1993-04-02 Nec Corp Gate bias control circuit

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