JPS61161025A - Circuit for detecting code rule violation - Google Patents
Circuit for detecting code rule violationInfo
- Publication number
- JPS61161025A JPS61161025A JP138585A JP138585A JPS61161025A JP S61161025 A JPS61161025 A JP S61161025A JP 138585 A JP138585 A JP 138585A JP 138585 A JP138585 A JP 138585A JP S61161025 A JPS61161025 A JP S61161025A
- Authority
- JP
- Japan
- Prior art keywords
- rule violation
- signal
- logical
- code rule
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Error Detection And Correction (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はコーデドマークインバージョン（以下ＣＭＩと
記す）符号等に用いることができる符号則違反検出回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a code rule violation detection circuit that can be used for coded mark inversion (hereinafter referred to as CMI) codes and the like.
（従来の技術）
第３図は従来のＣＭＩ符号則違反検出回路の構成の一例
を示す図である。(Prior Art) FIG. 3 is a diagram showing an example of the configuration of a conventional CMI code rule violation detection circuit.
なお、以下ＣＭＩ符号化データは第２図の如く符号化す
るものとする。It is assumed that the CMI encoded data is encoded as shown in FIG. 2 below.
つまり、 ＮＲＺデータの“１″は“１１”、”００”
に対応し、この２つの状態は交互に送出され、 ＮＲＺ
符号の“０”は“１０”に対応する。In other words, “1” in NRZ data is “11”, “00”
These two states are sent out alternately, corresponding to NRZ
The code "0" corresponds to "10".
以下、第３図に戻っ工従来のＣＭＩ符号則違反検出回路
についてその動作を説明する。なお、信号波形について
は第２図に従い説明する。The operation of the conventional CMI code rule violation detection circuit will now be described with reference to FIG. Note that the signal waveform will be explained according to FIG.
第３図において、１はＡＮＤゲート、２はシフトレジス
タ（立下り動作）、３．４はＥｘ−ＯＲゲート、５はＮ
ＡＮＯゲートを示し、６はＣＭＩ符号化データ、７はＮ
ＲＺデータ、８はクロック信号、９はＣＭＩ符号則違反
検出信号である。In Figure 3, 1 is an AND gate, 2 is a shift register (falling operation), 3.4 is an Ex-OR gate, and 5 is an N gate.
ANO gate is shown, 6 is CMI encoded data, 7 is N
RZ data, 8 is a clock signal, and 9 is a CMI code rule violation detection signal.
クロック信号８はＮＲＺデータ７が１１１１７の時のみ
シフトレジスタ２に入力される。これによりシフトレジ
スタ２の出力１５〜１８の出力Ｑ、〜Ｑ、には、通常１
１００．００１１が出力されることになる。よって、
ＣＭＩ符号則違反検出信号９は通常″゛Ｏ”である。Clock signal 8 is input to shift register 2 only when NRZ data 7 is 11117. As a result, outputs Q, ~Q, of outputs 15 to 18 of shift register 2 normally have 1
100.0011 will be output. Therefore,
The CMI code rule violation detection signal 9 is normally "O".
何らかの原因でＮＲＺデータ７がｉｔ １ ｔｓの時に
ＣＭＩ符号化データ６が上記繰返しに異常をきたした時
、つまり、１１１１又はｏｏｏｏに変化した場合、ＣＭ
Ｉ符号則違反検出信号９は１″を示すようになる。When NRZ data 7 is it 1 ts for some reason and CMI encoded data 6 becomes abnormal in the above repetition, that is, when it changes to 1111 or oooo, CM
The I sign rule violation detection signal 9 comes to indicate 1''.
しかし上記構成では、電源投入後のシフトレジスタ２の
初期値によってはＣＭＩ符号則違反検出信号９が’１″
（符号則違反の状態を示す）になり、この後、 ＮＲＺ
データが長期間“０〃を示す場合は、シフトレジスタ２
の出力１５〜１８は変化し得ないので。However, in the above configuration, depending on the initial value of the shift register 2 after the power is turned on, the CMI code rule violation detection signal 9 is '1'.
(indicates a violation of the code rules), and after this, NRZ
If the data shows “0” for a long period of time, shift register 2
Since the outputs 15-18 of cannot change.
ＣＭＩ符号則違反検出信号９も長期間“１″を示すこと
になる。The CMI code rule violation detection signal 9 also shows "1" for a long period of time.
（発明が解決しようとする問題点）
上記のように、従来のＣＭＩ符号則違反検出回路では、
電源投入後ＮＲＺデータが“１”の状態を２回受信する
までＣＨＩ符号則違反検出回路は異常な出力を示す可能
性がある。(Problems to be Solved by the Invention) As mentioned above, in the conventional CMI coding rule violation detection circuit,
After the power is turned on, the CHI code rule violation detection circuit may exhibit an abnormal output until the NRZ data receives the "1" state twice.
本発明はかかる点に鑑みてなされたもので、電源投入後
ＣＨＩ符号則違反検出信号が異常な出力を示さないよう
な符号則違反検出回路を提供することを目的としている
。The present invention has been made in view of the above problems, and an object of the present invention is to provide a coding rule violation detection circuit in which the CHI coding rule violation detection signal does not exhibit an abnormal output after power is turned on.
（問題点を解決するための手段）
本発明は上記問題点を解決するため、電源投入後“′１
″又は“Ｏ”の同一符号を少なくとも２回以上受信する
まで、符号則違反検出を行なわない機能を有するもので
ある。(Means for Solving the Problems) In order to solve the above problems, the present invention aims to solve the problems described above.
It has a function of not detecting a violation of the code rule until the same code of "" or "O" is received at least twice.
（作用）
本発明は上記した構成により、符号則違反検出回路の内
部状態が、異常な符号則違反検出信号を出力しないよう
な状態となるまで、符号則違反検出を行なわないので、
上記従来の欠点を補正することができる。(Function) With the above-described configuration, the present invention does not perform coding rule violation detection until the internal state of the coding rule violation detection circuit becomes such that it does not output an abnormal coding rule violation detection signal.
The above conventional drawbacks can be corrected.
（実施例）
第１図は本発明の符号則違反検出回路の一実施例を示す
構成図である。なお、信号波形については第２図に従い
説明する。(Embodiment) FIG. 1 is a block diagram showing an embodiment of the code rule violation detection circuit of the present invention. Note that the signal waveform will be explained according to FIG.
ここで、第２図は本発明の一実施例及び従来例の符号則
違反検出回路の要部波形図である。Here, FIG. 2 is a waveform diagram of essential parts of an embodiment of the present invention and a conventional coding rule violation detection circuit.
第１図において１〜２７は第３図で示したものと同じで
あり、２８はＡＮＤゲート、２９はＯＲゲート、３０は
ＮＯＲゲート、３１はプリセッタブルネガティブゴーイ
ングダウンカウンタ（以下カウンタと略す）。In FIG. 1, 1 to 27 are the same as those shown in FIG. 3, 28 is an AND gate, 29 is an OR gate, 30 is a NOR gate, and 31 is a presettable negative going down counter (hereinafter abbreviated as counter).
４７はバッファ、５０は抵抗、５１はコンデンサ、５４
は接地点、５５は電源を示す。47 is a buffer, 50 is a resistor, 51 is a capacitor, 54
indicates a grounding point, and 55 indicates a power source.
電源５５が投入されると、抵抗５０．コンデンサ５１で
構成される積分回路により、成る期間カウンタ３１のプ
リセットイネーブル４１の端子はしとなり、カウンタ３
１のプリセット入力３９，４０，５２で設定される値（
ここでは４）を設定する。When the power supply 55 is turned on, the resistor 50. The integrator circuit constituted by the capacitor 51 serves as the terminal of the preset enable 41 of the period counter 31.
1 preset inputs 39, 40, and 52 (
Here, 4) is set.
この時ＡＮＤゲート２８の入力３３には“０″が出力さ
れ、ＣＭＩ符号則違反検出信号９はシフトレジスタ２の
出力１５〜１８がどのような状態にあろうとも“０”（
ＣＭ工符号則違反が発生していないことを示す、）とな
る、このＣＨＩ符号則違反信号９が強制的に０”を示す
状態は、クロック信号８゛にクロックパルスが４発送出
されるまで続く。At this time, “0” is output to the input 33 of the AND gate 28, and the CMI code rule violation detection signal 9 is “0” (
This state in which the CHI code rule violation signal 9 forcibly indicates 0'' continues until 4 clock pulses are sent to the clock signal 8', indicating that no CM code rule violation has occurred. .
この状態になるとＡＮＤゲート２８の入力３３は“１”
になり、入力３２への入力信号を受は付けることになる
。つまり、ＣＭＩ符号則違反検出がイネーブルとなる。In this state, the input 33 of the AND gate 28 is “1”
This means that the input signal to the input 32 is accepted. In other words, CMI code rule violation detection is enabled.
この時ＣＭＩ符号則違反検出信号は、シフトレジスタ２
の出力１５〜１８にはＮＲＺデータ７が“１″の時の値
に揃うので正常な信号となる。At this time, the CMI code rule violation detection signal is the shift register 2
The outputs 15 to 18 of the outputs 15 to 18 have the same values as when the NRZ data 7 is "1", so they are normal signals.
（発明の効果）
以上説明したように、本発明によれば、電源投入後符号
則違反検出信号が正常な値を示すまで、出力信号を強制
的に、符号則違反検出信号を禁止するので、実用的に極
めて有用である。(Effects of the Invention) As explained above, according to the present invention, the output signal is forcibly output and the coding rule violation detection signal is prohibited until the coding rule violation detection signal shows a normal value after power is turned on. It is extremely useful in practical terms.
第１図は本発明の符号則違反検出回路の一実施例を示す
構成図、第２図は本発明の一実施例及び従来例の符号則
違反検出回路の要部波形図、第３図は従来のＣＭＩ符号
則違反検出回路の構成の一例を示す図である。
２ ・・・シフトレジスタ、７ ・・・ＮＲＺデータ。
８ ・・・クロック信号、９ ・・・ＣＨＩ符号則違反
信号、２８・・・ＡＮＤゲート、３１・・・カウンタ。
３２．３３・・・ＡＮＤゲート２８の入力。
３９．４０．５２・・・カウンタ３１のプリセット入力
。
５０・・・抵抗、５１・・・コンデンサ。
特許出願人 松下電器産業株式会社
第２図
一時間FIG. 1 is a block diagram showing an embodiment of the coding rule violation detection circuit of the present invention, FIG. 2 is a waveform diagram of main parts of the coding rule violation detection circuit of the embodiment of the invention and the conventional example, and FIG. 3 is a block diagram showing an embodiment of the coding rule violation detection circuit of the present invention. 1 is a diagram illustrating an example of the configuration of a conventional CMI code rule violation detection circuit. 2...Shift register, 7...NRZ data. 8...Clock signal, 9...CHI code rule violation signal, 28...AND gate, 31...Counter. 32.33...Input of AND gate 28. 39.40.52...Preset input for counter 31. 50...Resistor, 51...Capacitor. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 2 1 hour
Claims (1)
回以上受信するまで、符号則違反検出を行なわない機能
を有することを特徴とする符号則違反検出回路。After turning on the power, the same code of “1” or “0” is displayed at least twice.
1. A coding rule violation detection circuit having a function of not detecting a coding rule violation until reception is received more than once.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP138585A JPS61161025A (en) | 1985-01-10 | 1985-01-10 | Circuit for detecting code rule violation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP138585A JPS61161025A (en) | 1985-01-10 | 1985-01-10 | Circuit for detecting code rule violation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61161025A true JPS61161025A (en) | 1986-07-21 |
Family
ID=11500015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP138585A Pending JPS61161025A (en) | 1985-01-10 | 1985-01-10 | Circuit for detecting code rule violation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61161025A (en) |
-
1985
- 1985-01-10 JP JP138585A patent/JPS61161025A/en active Pending
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