JP2549152B2 - Code error detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial field of use Conventional technology Problems to be solved by the invention Means for solving the problem Action Example I. Correspondence between Example and FIG. 1 II Configuration of Embodiment (i) Overall Configuration (ii) Configuration of Mask Pulse Generation Circuit III. Operation of Embodiment IV. Summary of Embodiment V. Modification of Invention Effect of Invention [Overview] Bipolar coded Regarding a code error detection circuit for monitoring a communication code error, for the purpose of accurately detecting a code error, a violation detection means for detecting a code rule violation of a bipolar encoded input signal, and a detection signal of the violation detection means A mask pulse generating means for generating a mask pulse of a predetermined length based on, a discriminating means for discriminating a coding rule violation detected by the violation detecting means as a coding rule violation, while the mask pulse is generated, With Configured to detect a code error of the signal.

[Industrial applications]

The present invention is based on, for example, B8ZS among the bipolar encoding methods.
Method, B6ZS method, such as a code error detection circuit for monitoring communication coded by a coding method that intentionally applies a code that violates the coding rule to predetermined data, and in particular, a code intentionally inserted The present invention relates to a code error detection circuit that does not detect a rule violation.

[Conventional technology]

Data to be communicated in digital communication is transmitted after being encoded so as to be suitable for transmission on a communication line. As one of the encoding methods, there is a bipolar encoding method, and in principle, adjacent "1" s in data to be communicated are indicated by alternately applying codes of different polarities. Codes of such different polarities will be called bipolar bits (B bits).

FIG. 6 is an explanatory diagram of data encoded by the bipolar encoding method.

For example, the code indicating the 8-bit data "10011010" is "B00BB0B0" as shown in FIG.

As described above, since the data to be communicated is encoded so that pulses of the same polarity do not continue, the coding rule violation detection circuit on the receiving side continuously outputs bits of the same polarity as shown in FIG. Then, it is detected as a code error caused by noise on the transmission path.

Such a code rule violation is called a bipolar violation, and a code rule violation bit is called a violation bit (V bit).

In a terminal device that relays and monitors communication through a communication line, a code rule violation detection circuit for detecting a code error as described above and a code rule violation detected by the code rule violation detection circuit are detected for a predetermined time T. There is provided an error determination unit that determines whether or not it is an obstacle for continuing communication based on the number (violation rate).

The error determination unit has a violation rate R _V
When it exceeds the threshold, it is determined that the input signal input to the terminal device is incorrect because an abnormality has occurred in the communication line or the terminal device, and an alarm is issued to the subsequent device such as the decoding unit.

After outputting this alarm, the error determination unit further measures the violation rate a predetermined number of times, and if the result is always less than or equal to the predetermined number R _V , it is determined that the input signal is correct, and the input signal is processed. Resume.

By the way, some of the bipolar encoding methods, such as the B8ZS method and the B6ZS method, correspond to consecutive “0” bits included in the data when encoding communication data, and violate the coding rule. There is a method of outputting a predetermined code that intentionally includes a relative bit (V bit).

For example, an encoding device based on the B8ZS system outputs "000VB0VB" as shown in FIG. 6 in response to 8 consecutive "0s" in the data. Upon receipt of this communication data, the coding rule violation detection circuit on the receiving side does not detect the violation bit included in the communication data as a code error, and interprets it as a continuous “0” of 8 bits.

On the other hand, communication data (0
(See FIG. 6) is transmitted after being transformed as shown in FIG. 6, the original code error (1
In addition to (bit), two intentionally entered violation bits are also detected as code errors.

[Problems to be Solved by the Invention]

By the way, in the above-mentioned conventional coding rule violation detection circuit, all the coding rule violations included in the communication data are detected as code errors due to noises, etc. Therefore, a larger number of codes than actual code errors are generated. There is a problem that an error is detected and the number of code errors cannot be correctly grasped.

In this way, when the code violation detection circuit cannot correctly grasp the number of code errors and detects a larger number of code errors than the actual one, in order to meet the demand for improvement of communication quality, the code error tolerance of the terminal device is tolerated. When the range is set small, it is possible that the error determination unit frequently outputs an alarm and the communication process is temporarily stopped.

Also, when setting the allowable range of code error to be small,
The time T for accumulating code errors is set longer than before. For this reason, the time required for the error determination unit to determine whether or not the input signal is truly abnormal becomes long, and the time during which the terminal device is temporarily stopped becomes long.

The present invention has been made in view of such a point, and provides a code error detection circuit for accurately detecting a code error without detecting a deliberately entered violation bit as a code error. The purpose is to do.

[Means for solving the problem]

FIG. 1 is a block diagram of the principle of the code error detection circuit of the present invention.

In the figure, a violation detecting means 101 detects a coding rule violation of a bipolar-coded input signal.

The mask pulse generation means 102 generates a mask pulse of a predetermined length based on the detection signal of the violation detection means 101.

The determination means 103 is a period during which the mask pulse is generated,
It is determined that the coding rule violation detected by the violation detection means is not a coding rule violation.

[Work]

When the violation detection means 101 detects a code rule violation of the input signal, the mask pulse generation means 102 generates a mask pulse of a predetermined length based on the detection signal.

The determination means 103 determines whether or not the detection signal corresponds to a deliberately entered code rule violation, based on the detection signal from the violation detection means 101 and the mask pulse output state of the mask pulse generation means 102.

In the present invention, since the detection signal indicating the coding rule violation intentionally entered is discriminated, it is not output as a code error and the code error of the signal can be accurately detected.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of the communication monitoring section using the code error detection circuit in one embodiment of the present invention.

I. Correspondence between Embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be described.

The violation detection means 101 corresponds to the coding rule violation detection circuit 201.

The mask pulse generating means 102 is a mask pulse generating circuit 2
Equivalent to 10.

 The discrimination means 103 corresponds to the OR gate 203.

An embodiment of the present invention will be described below on the basis of the above correspondence.

II. Configuration of Embodiment (i) Overall Configuration of Communication Monitoring Unit In FIG. 2, the communication monitoring unit using the code error detection circuit in the embodiment violates the coding rule from the input bipolar signals. A code rule violation detection circuit 201 that detects a pulse (violation bit), and a mask pulse generation circuit 210 that generates a mask pulse having a length of three cycles of a clock signal based on a detection signal of the code rule violation detection circuit 201. , A logical sum gate that takes the logical sum of the detection signal and the mask pulse output by the mask pulse generation circuit 210
203 and an error determination section 240 that measures the violation rate based on the error detection signal output from the OR gate 203 and outputs an alarm based on the result.

The error determination unit 240 includes a counter 242 that accumulates an error detection signal, a timer 241 that limits the accumulation time of the error detection signal by the counter 242 to a predetermined time T, and a communication line based on the violation rate accumulated in the counter 242. And a determination unit 243 that determines whether or not there is an abnormality.

Here, it is assumed that the input signal is input in synchronization with the clock signal.

(Ii) Configuration of Mask Pulse Generation Circuit FIG. 3 is a configuration diagram of the mask pulse generation circuit 210 in the embodiment shown in FIG.

In the figure, a mask pulse generation circuit 210 includes a logical sum gate 211 that performs a logical sum of a clock signal and a detection signal of the code rule violation detection circuit 201, NAND gates 214a and 214b that form a latch circuit, and a logical sum gate 211. Is used as a clock (CK) input to output a set input signal of the latch circuit, an inverter 213 that inverts the output of the NAND gate 214a and clears the flip-flop 212, and a timer 3 It is formed of two flip-flops 215a, 215b, 215c.

The output terminal of the flip-flop 212 is a NAND gate 214
It is connected to one of the input terminals of b, the power supply voltage is input to the input terminal D, and is always in the "1" state.

The other input terminal of the NAND gate 214b is connected to the output terminal of the NAND gate 214a and the input side of the inverter 213, and the output terminal of the NAND gate 214b is clear (CL) of the flip-flops 215a, 215b, 215c of the NAND gate 214a. It is connected to one of the terminal and the input terminal. The flip-flop 21 is connected to the other input terminal of the NAND gate 214a.
The output terminal of 5c is connected.

Clock signals are input to the clock (CK) terminals of the flip-flops 215a, 215b, and 215c, respectively, and the power supply voltage is input to the input terminal D of the flip-flop 215a. The output terminal Q of the flip-flop 215a is connected to the input terminal D of the flip-flop 215b, and the output terminal Q of the flip-flop 215b is the flip-flop 215c.
Is connected to the input terminal D.

III. Operation of the Embodiment FIGS. 4 and 5 are timing charts for explaining the operation of the embodiment shown in FIG.

The operation of the embodiment will be described below with reference to FIGS.

In Fig. 4, a signal obtained by encoding 8-bit consecutive "0s" by the B8ZS system (see Fig. 4) is mixed with pulses of polarity "+" in the 0th bit due to noise during transmission. The received signal when transmitted is shown.

When such a signal is input to the code rule violation detection circuit 201, a code rule violation is detected in the 0th bit, the 3rd bit and the 6th bit, and a detection signal as shown in FIG. 4 is output.

Here, the input signal (see FIG. 4) is assumed to be input in synchronization with the clock signal shown in FIG.

The detection signal and the clock signal input to the mask pulse generation circuit 210 are ORed by the OR gate 211 (see FIG. 4) and input to the clock (CK) terminal of the flip-flop 212.

When the output of the OR gate 211 rises, the output terminal of the flip-flop 212 is reversed to "0" (see FIG. 4).
Becomes On the other hand, since the flip-flop 215c is cleared, the input to the latch circuit formed by the NAND gate 214a and the NAND gate 214b becomes "1" on the NAND gate 214a side and "0" on the 214b side, and the latch circuit is reset. , The output of the NAND gate 214b (that is, the mask pulse) rises (see FIG. 4).

Flip-flops 215a, 215b, 21 by mask pulse
Since the clear of 5c is released, the flip-flops 215a, 2f are set at the rising edge of the clock signal (see FIG. 4).
"1" is set to each output terminal Q in the order of 15b and 215c.

The output terminal of the flip-flop 215c becomes "0" at the rising edge of the third clock signal after the clear is released. As a result, the output of the NAND gate 214a becomes "1", the polarity of which is inverted by the inverter 213 and the flip-flop 212 is cleared.
The 12 output terminals are "1" (see Fig. 4).

Input to the latch circuit is “0”, 2 on the NAND gate 214a side.
Since the 14b side becomes "1", the latch circuit is set,
Since the output of the NAND gate 214b becomes "0", the mask pulse falls (see FIG. 4). Also, the flip-flops 215a, 215b, 215c are cleared again.

In this manner, the mask pulse generation circuit 210 detects the first 3
A mask pulse for a period (see FIG. 4) is output.

The logical sum gate 203 takes the logical sum of the violation pulse shown in FIG. 4 and the mask pulse shown in FIG. 4 to obtain an error detection signal (shown in FIG. 4).

Therefore, the violation pulse corresponding to the third bit detected by the coding rule violation detection circuit 201 is deleted within three cycles of the clock after the first violation pulse. However, since the violation pulse corresponding to the 6th bit is not deleted, the code error is regarded as two, which is one more than the true code error.

By the way, if the detection signal of the coding rule violation detection circuit 201 is deleted by the mask pulse described above, the detection signal indicating a true code error may be deleted as well.

For example, when the signal as shown in FIG. 5 is input to the code rule violation detection circuit 201, the code violation detection signal becomes as shown in FIG.

The mask pulse generated by the mask pulse generation circuit 210 is as shown in FIG.
The code error detection signal output from 203 is as shown in FIG. 5, and only two code errors smaller than the original code error are detected.

However, as shown in FIG. 5, the probability of receiving a signal in which three consecutive pulses of the same code remain due to a code error is small.

On the other hand, if the length of the mask pulse is extended to, for example, the length of six clock cycles, the violation pulse corresponding to the sixth bit can also be deleted. However, if the mask pulse is lengthened in this way, the probability of deleting the violation pulse corresponding to the true code error increases accordingly.

In consideration of these matters, the length of the mask pulse is set to three clock cycles in the embodiment.

The error detection signal obtained as described above is input to the error determination unit 240 and accumulated in 242 for a predetermined time T set in the timer 241.

When the number of error detection signals (violation rate) accumulated in 242 becomes a predetermined value R _V or more, the determination unit 243 determines that
An alarm is output when it is judged that an abnormality may have occurred in the communication line or the terminal device.

After that, the error determination unit 240 further measures the violation rate a predetermined number of times. As a result, if the violation rate is always within the allowable range, it is determined that there is no abnormality in the communication line or the terminal device.

On the other hand, when the measurement result of the violation rate always exceeds the allowable range, it is determined that the communication line or the terminal device is truly abnormal.

IV. Summary of Embodiments As described above, the detection signal of the violation detected by the coding rule violation detection circuit 201 is detected by the mask pulse having the length of three cycles of the clock output by the mask pulse generation circuit 210. To mask.

Therefore, even when the coding rule violation detection circuit 201 intentionally detects a violation that is included in the code as a code error, the coding rule violation detection circuit 20 corresponding thereto is detected.
It is possible to delete at least one bit of the violation pulse from the one detection signal.

As a result, the code error detection circuit can accurately grasp the number of code errors and monitor the communication, so that it is possible to prevent the terminal device from frequently stopping its operation.

V. Modified Embodiment of the Invention In the above-described embodiment of the present invention, the case where the detection signal is deleted by the mask pulse having the length of three clock cycles is considered, but the present invention is not limited to this. Any method can be applied as long as the detection signal is deleted by the mask pulse of length.

In addition, in “I. Correspondence between Example and FIG. 1”,
Although the correspondence between the present invention and the embodiments has been described, the present invention is not limited to this, and those skilled in the art can easily contemplate that the present invention has various modifications.

〔The invention's effect〕

As described above, according to the present invention, the detection signal corresponding to the code rule violation intentionally inserted in the code is discriminated and deleted by the mask pulse having the predetermined length.

As a result, it is possible to accurately grasp the number of code errors and monitor the communication. For example, it is possible to prevent the operation of the terminal device from frequently stopping, which is extremely useful in practice. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of a code error detecting circuit according to the present invention, FIG. 2 is a block diagram showing a code error detecting circuit according to an embodiment of the present invention, and FIG. 3 is according to the embodiment shown in FIG. FIG. 4 is a timing diagram showing the operation of the code error detection circuit according to the embodiment shown in FIG. 2, and FIG. 5 is a view showing the mask pulse generation circuit of the code error detection circuit according to the embodiment shown in FIG. FIG. 6 is a timing diagram showing the operation of the code error detection circuit, and FIG. 6 is an explanatory diagram of the bipolar code. In the figure, 101 is a violation detecting means, 102 is a mask pulse generating means, 103 is a determining means, 201 is a code rule violation detecting circuit, 210 is a mask pulse generating means, 203 is an OR gate, 240 is an error determining section, 211 is 211 An OR gate, 212 and 215 are flip-flops, 213 is an inverter, 214 is a NAND gate, 241 is a timer, 242 is a counter, and 243 is a judgment unit.

Claims (1)

(57) [Claims] 1. Violation detection means for detecting a coding rule violation of a bipolar-encoded input signal, and mask pulse generation means for generating a mask pulse of a predetermined length based on a detection signal of the violation detection means. A period in which the mask pulse is being generated, a determination unit that determines that the code rule violation detected by the violation detection unit is not a code rule violation, and is configured to detect a code error in a signal. A code error detection circuit characterized by the above.