GB2147477A - Data transmitter, data receiver and data transmission system - Google Patents

Abstract

A data transmission system includes a transmitter in which a data signal (1a) is encoded to form a Miller coded signal (1b) which is then differentiated (1e) before being fed to a transmission link, for example a telephone line. Narrow bandwidth lines tend to integrate the signal passed along them (1g) and the original Miller coded signal may be extracted by means of a level sensitive detector. On short lines the differentiated signal is received but this is decodable by use of the same level sensitive detector (1i). Passive differentiation (1e) leads to inefficiencies in the transmitter and it is therefore preferable to perform a pseudo differentiation by producing short pulses of alternating polarity for each level change (1f). A data transmitter and data receiver for a pseudo-differentiated Miller coded data signal are described. <IMAGE>

Description

SPECIFICATION Data transmitter data receiver and data transmission system The invention relates to a data transmitter comprising means for generating a transmission code from binary data, the transmission code having two levels with abrupt transitions between those levels.

The invention further relates to a data receiver for receiving and decoding such transmission codes and to a data transmission system comprising such data transmitters and receivers and a signal transmission medium.

There is an increasing requirement for the transmission of data over telephone lines, for example from data terminals to a central computer. It is clearly advantageous to effect this transmission at as high a signalling rate as possible in order to maximise the quantity of information which can be conveyed in a given time. However, it is also desirable to be able to use standard telephone lines which have a bandwidth of 3.4 KHz. It is possible to transmit data at higher rates using appropriate digital processing techniques in the receiver but it is desirable to limit the high frequency content of the transmitted signal as far as possible. A number of transmission codes have been proposed each of which may have advantages in a particular system. One of these codes is known as Miller code or delay modulation and has a spectral peak at half the bit rate.However this code suffers from the disadvantage that certain bit patterns can produce a d.c. component in the transmitted signal.

It is an object of the invention to enable the provision of a data transmitter which produces a transmission code having no d.c. component.

The invention provides a data transmitter as set forth in the opening paragraph characterised by means for generating a short duration pulse at each level transition, the pulses being of alternating polarity with respect to a reference level and means for applying the pulses to a transmission link.

It has been found that the narrow bandwidth telephone lines cause the transmitted signal to be integrated and that consequently it is necessary to differentiate the received signal to recover the original waveform. If the signal to be transmitted is differentiated prior to transmission then on long lines the receiver receives a signal which is substantially in the form of the original signal before differentiation as the limited bandwidth line integrates the signal passed along it. On short lines the signal at the receiver is still in the differentiated form. Both these signals may be decoded in the receiver by applying them to a level sensitive detector, such as a Schmitt trigger circuit. The short duration pulses are effectively a differentiated form of the transmission code.The differentiated version of the Miller code has the advantage that there is no d.c. component regardless of the bit pattern. It is preferable to produce the effective differentiation of the transmission code by producing short pulses by means of logic circuits since passive differentiation produces an inefficiency in the output stage of the transmitter.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which Figure 1 shows binary data encocied in various codes for transmission and the effect of various length narrow band transmission links on the encoded data; Figure 2 shows a data transmitter according to the invention; Figure 3 shows signals at various points in the transmitter shown in Figure 2; Figure 4 shows a receiver for receiving the signal generated by the transmitter shown in Figure 2, Figure 5 shows signals at various points in the receiver shown in Figure 4, and Figure 6 shows in block schematic form a data transmission system according to the invention.

Figure 1 a) shows a binary signal representing the code shown while Figure 1 b) shows the binary signal of Figure la) encoded into the Miller code. Figure 1c) shows the Miller coded signal after passing down a long line.

From Figure 1c) it can be seen that certain bit patterns produce a d.c. level shift in the signal received at the end of a line. Figure 1 d) shows the signal of Figure 1 c) when differentiated to recover the original encoded signal while Figure 1 e) shows the signal of Figure 1 b) differentiated. Figures 1 d) and 1 e) illustrate the received signal after differentiation when received over long and short lines respectively.

Figure 1 f) shows a binary code encoded for transmission by a transmitter according to the invention. The transmission code comprises a short positive going pulse for each positive going transition and a short negative going pulse for each negative going transition. By encoding the data to be transmitted in this way the d.c. level shift produced by certain bit patterns in the Miller code is eliminated since the duration of all the pulses is constant and the pulses are alternately positive and negative. Figure 1 g) shows the effect of transmission down a long line of restricted bandwidth on the signal shown in Figure 1f) while Figure 1 i) shows the signal of Figure 1 f) when received over a short line.Figures 1h) and 1j) show the effect of level detection of the signals shown in Figures 1 g) and 1 i) as achieved, for example, by applying these signals to a Schmitt trigger circuit. As can be seen the signals shown in Figures 1h) and 1j) are reconstructions of the Miller coded signal shown in Figure 1 b).

Figure 2 shows a transmitter for producing a transmission code as shown in Figure 1f) from an input data signal as shown in Figure 1 a). A clock signal at the same rate as the bit rate of the input data signal is applied to a terminal 1 while the input data signal is applied to a terminal 2. The terminal 1 is connected to a first input of an AND gate 3, to the input of an inverter 4, and to the clock input of a D-type bistable circuit 5. The terminal 2 is connected to the D input of the bistable circuit 5 while the output of the inverter 4 is connected to a first input of an AND gate 6. The Q and Q outputs of the bistable circuit 5 are connected to second inputs of the AND gates 3 and 6 respectively.

The outputs of the AND gates 3 and 6 are connected to first and second inputs of an OR gate 7 whose output is connected to a trigger input of a pulse generator 8. The output of the pulse generator 8 is connected to the input of a divider 9 and to first inputs of two AND gates 10 and 11. A first output of the divider 9 is connected to a second input of the AND gate 10 while a second output of the divider 9 is connected to a second input of the AND gate 11. The output of AND gate 10 is connected through an inverter 1 2 to one end of a resistor R1 the other end of which is connected to the junction of a resistor R2, a resistor R3 and the base of a pnp transistor T1. The resistors R2 and R3 are connected in series between positive and negative supply rails. The output of AND gate 11 is connected through a resistor R4 to the junction of resistors R2 and R3.The emitter of transistor T1 is connected to the positive supply rail via a resistor R5 while its collector is connected via a resistor R6 to the negative supply rail and via a capacitor C1 to an output terminal 1 3.

In operation a data signal such as that shown in Figure 3a) is applied to input terminal 2 while a clock signal such as that shown in Figure 3b) is applied to input terminal 1.

Thus the AND gate 3 has the clock signal applied to its first input while the AND gate 6 has an inverted clock signal as shown in Figure 3c) applied to its first input, the clock signal also being applied to the bistable circuit 5. As a result of the application of these signals the OR gate 7 produces a signal as shown in Figure 3d). If the signal produced at the output of OR gate 7 is fed to a divide-bytwo circuit then the Miller coded version of the input data signal will be produced at its output. In the transmitter shown in Figure 2 the output of the OR gate 7 is fed to the trigger input of the pulse generator 8 which produces a short pulse starting at each positive going transition of the OR gate output.

The output signal produced by the pulse generator 8 is shown in Figure 3e). This signal is applied to a binary divider 9 whose outputs, which take the form shown in Figure 39) and h), are connected to the AND gates 10 and 11 together with the pulse generator output.

This results in the signals shown in Figure 3i) and j) being produced at the outputs of the AND gate 11 and inverter 1 2. When both these signals are positive the output signal at terminal 1 3 is at a peak negative value, when both these signals are negative the output signal at terminal 1 3 is at a peak positive value, and when one of the signals in negative while the other is positive the output signal at terminal 1 3 is at an intermediate value. Thus the signal shown in Figure 3f) is produced at the output terminal 1 3 and provides a transmission code having no d.c.

component since the positive and negative pulses are balanced.

While the transmitter illustrated in and described with reference to Figure 2 of the accompanying drawings has been designed to further encode a Miller coded signal for transmission over a transmission line any other two level transmission code could be treated in the same manner i.e. short pulses of alternate polarity generated for each level transition. With some transmission codes it may be necessary to ensure that positive going transitions are matched by positive going pulses and vice versa, but this is frequently unnecessary since it is normally desirable that a knowledge of the polarity of the received signal should be unnecessary for decoding the received signal.

Figure 4 is a block diagram of a data receiver for use in a data transmission system according to the invention and Figure 5 illustrates waveforms at various points within the receiver. The receiver has an input terminal 100 for receiving the transmitted data signal and coupling it via a capacitor 101 to the input of a level sensing circuit 102 which may take the form of a Schmitt trigger circuit. The output of the level sensing circuit 102 is fed via a first path to the input of an edge detector 103, via a second path to the input of a clock extraction circuit 104, via a third path to the D input of a D-type bistable circuit 105, and via a fourth path to a first input of an exclusive-OR gate 106. The output of the edge detector 103 is fed to a reset input of a counter 107 while the output of the clock extraction circuit 104 is fed to the clock inputs of the counter 107, the D-type bistable 105, and a divide-by-two circuit 108. The Q output of the D-type bistable 105 is fed to a second input of the exclusive-OR gate 106 while the output of the exclusive-OR gate 106 is fed to D inputs of two further D-type bistable circuits 109 and 110.The Q output of the divide-by-two circuit 108 is connected to the clock input of the bistable 109 while the Q output is connected to the clock input of the bistable 110. The Q outputs of the bistables 109 and 110 are connected to first inputs of respective AND gates 111 and 11 2 while the Q outputs are connected to first inputs of respective NAND gates 11 3 and 114. The outputs of the NAND gates 11 3 and 114 are connected to first inputs of respective NAND gates 11 5 and 11 6 which are interconnected to form an R.S. bistable circuit.The output of NAND gate 11 5 is connected to a second input of AND gate 111 while the output of NAND gate 11 6 is con nected to a second input of AND gate 11 2.

The outputs of AND gates 111 and 112 are connected to first and second inputs of an OR gate 11 7 whose output is connected to a terminal 11 8 at which the decoded data signal becomes available. An output of the counter 107 is connected to a first input of a NAND gate 119 which is interconnected with a further NAND gate 1 20 to form an RS bistable circuit, the first input of the NAND gate 11 9 forming the set input of the bistable circuit.The output of the NAND gate 11 9 is connected to the D input of a D-type bistable circuit 121 whose 0 output is connected to second inputs of NAND gates 11 3 and 114 and to a first input of a NAND gate 1 22 whose output is connected to the reset input of the RS bistable circuit, the reset input being an input of the NAND gate 120. The clock signal from the clock extraction circuit 104 is fed to the clock input of the D-type bistable circuit 121 and via an inverter 123 to a second input of the NAND gate 1 22.

In operation a transmitted signal of the form shown in Figure 1f) which depending on the length of line over which it is transmitted before being applied to input terminal 100 may be of the form shown in Figure 1 g) or Figure li) is passed via the capacitor 101 to the input of the level sensing circuit 102.

Figure 5c) shows the form of the output of the level sensing circuit 102 for data as specified in Figure 1 a) or 1 b). This output is fed to the edge detector 103 whose output resets the counter 107 whenever a level change is detected in the output of the level sensing circuit 102 and also to the clock extraction circuit 104 to synchronise the clock signal with the data bit periods. The clock extraction circuit 104 produces a clock signal having two cycles per bit period as shown in Figure 5d).

Assuming that the D-type bistable circuits 105, 109, and 110, the counter 107, and the divide-by-two circuit 108 are arranged to be clocked by the rising edge of the clock waveform, the clock waveform is arranged to have its rising edges one quarter and three quarters of the way through each bit period.

This may be achieved by phase locking the falling edge of the clock waveform with the transitions of the output of the level sensing circuit 102.

The data signal as shown in Figure 5c) is applied to the D input of the bistable 105 and appears at its Q output on the rising edge of the clock taking the form of the waveform shown in Figure 5e). This causes the waveform shown in Figure-Sf) to be produced at the output of the exclusive-OR gate 106. The waveforms shown in Figures 5g) and 5h) show the 0 and Q outputs of the divide-bytwo circuit 108 when fed with the clock signal shown in Figure 5d). The clock signal shown in Figure 5d) is generated by an oscil lator in a phase locked loop arrangement, the oscillator output being synchronised with the edges in the received data.With the clock phases as shown in Figure 5 the 0 output of the D-type bistable circuit 109 takes the form shown in Figure 5j). As can be seen from comparing Figures 5a) and i) the Q output of the bistable 109 is a true decoding of the received data and should therefore be passed through the AND gate 111 and OR gate 117 to the output terminal 11 8. The Q output of the D-type bistable 110 takes the form shown in Figure 51). As can be seen from comparing Figures 5b) and k) the 0 output of bistable 110 represents the data shown in Figure 5b).

However, in this case the detected bit periods are out of phase with the actual bit periods.

This can be deduced by the invalid state of the seventh bit period since there should have been a level transition in the received signal between the sixth and seventh bit periods if in fact two logic zeros were transmitted. Consequently the 0 output of the bistable 110 should not be allowed to pass through the AND gate 112 and OR gate 117 to the output 118.

It is not possible to be sure of the phases of the outputs of the divide-by-two circuit 108 with respect to the bit periods of the incoming data signal so it is necessary to provide a procedure for determining which of the D-type bistables 109 or 110 is correctly synchronised with the incoming data. To achieve this function a synchronising signal may be transmitted at given intervals, the synchronising signal taking the form shown in Figure 5m). As can be seen from comparing Figures 5m) and n) the synchronising signal is a Miller coded 1001 signal which has been corrupted by having the central transition suppressed.

The edge detector 103 produces a output at each detected level transition of the incoming signal, this output being applied to the counter 107 to reset its count to zero. The clock signal shown in Figure 5d) is applied to the clock input of the counter 107 and hence it counts the number of clock pulses occurring between each transition of the incoming signal. If a count of six is reached this is an indication that the synchronising signal has been transmitted and the counter output is fed to the set input of the RS bistable formed by the NAND gates 11 9 and 1 20 and on the occurrence of the next clock pulse causes the Q output of the D-type bistable 121 to go to a logic '1' thus enabling the NAND gates 113 and 114.At this time a data '1' should have been detected and hence it is necessary to determine which of the Q outputs of D-type bistables 109 and 110 is at a logic '1'. This is achieved by gating the 0 outputs of D-type bistables 109 and 110 with the Q output of the D-type bistable 121 in the NAND gates 11 3 and 114. If, for example, the Q output of D-type bistable 109 is at a logic '1' then the RS bistable formed by NAND gates 115 and 11 6 will be set by the Q output of D-type bistable 110 and consequently the AND gate 111 will be enabled thus selecting the output of the D-type bistable 109 as the correct data output signal.Conversely, if the Q output of D-type bistable 110 had been at a logic '1' then the RS bistable would have been reset and AND gate 11 2 enabled to select the output of the D-type bistable 110 as the correct data output signal.

If a count of greater than six is reached by the counter 107 this is an indication of a fault condition in the transmission system and may be used to initiate an alarm and/or to reset the receiver to an initial condition in a renewed attempt to detect the received data.

While in the receiver described with reference to Figure 4 it is necessary to determine the phase of a divided regenerated clock signal in order to correctly decode the received signal it is not necessary with all codes and all types of decoding to do so. Thus the transmitting and decoding of speciai synchronising signals will not always be necessary. Further other means of synchronising the clock and data may be used particularly with different transmission codes.

Figure 6 shows a data transmission system comprising a data transmitter 20, a data receiver 40 and a transmission link 30. The data transmitter 20 produces a signal which comprises a short duration pulse at each level transition of a transmission code having two levels with abrupt transitions between those levels, the pulses being of alternating polarity with respect to a reference level. This signal is applied to the transmission link 30, for example a transmission line or a radio link, over which it passes to the data receiver 40.

The data receiver 40 is arranged to receive the transmitted signal and decode it to obtain the transmitted data. The transmission system may operate in simplex, duplex or half-duplex modes. A duplex or half-duplex system will include a transmitter and a receiver at each end of the transmission link with a single transmission channel.

Claims (8)

1. A data transmitter comprising means for generating a transmission code from binary data, the transmission code having two levels with abrupt transitions between those two levels characterised by means for generating a short duration pulse at each level transition, the pulses being of alternating polarity with respect to a reference level, and means for applying the pulses to a transmission link.

2. A data transmitter as claimed in Claim 1 in which each positive going transition is transmitted as a positive going pulse and each negative going transition is transmitted as a negative going pulse.

3. A data transmitter as claimed in Claims 1 or 2 in which the transmissimn code is the Miller code.

4. A data transmitter substantially as described herein with reference to Figures 2 and 3 of the accompanying drawings.

5. A data transmission system including a data transmitter as claimed in any preceding claim, a data receiver and a transmission link between the data transmitter and data receiver.

6. A data transmission system including a data transmitter as claimed in Claim 3 and including a receiver which samples the incoming data twice in each bit period on each side of the centre of the bit period and compares the level of the detected transmission code in pairs in which, to enable the receiver decoder to be synchronised with the correct pair of samples a synchronising signal is transmitted.

7. A data transmission system as claimed in Claim 6 in which the synchronising signal comprises a Miller coded logic signal 1001 with the central transition suppressed.

8. A data receiver for a data transmission system as claimed in any of Claims 5 to 7, the data receiver being substantially as described herein with reference to Figures 4 and 5 of the accompanying drawings.