JPH07115442A - Decoding circuit for transmission line code - Google Patents

Abstract

PURPOSE:To detect all of one-bit errors by counting bipolar B pulses interposed between two violation V pulses and outputting the latter V pulse as the error detection pulse dependently upon whether the counted result is odd or even. CONSTITUTION:An ineffective V pulse detecting part 7 counts B pulses (bipolar pulses) interposed between two V pulses. When the counted result is odd, the latter of two V pulses is inhibited, and nothing is outputted. When it is even, the latter of two V pulses is outputted as the error detection pulse. That is, a zero continuity detecting part 4 detects the pattern of all 0s from contents of 4-bit shift registers 2 and 3. In the case of the NRZ code, contents of shift registers 2 and 3 cannot be all 0s because four bits of all 0s are certainly converted to the pattern of 000V or B00V in accordance with the HDB-3 code rule. Consequently, the error is detected by the detection result in the detecting part 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line code decoding circuit for decoding a transmission line code in which consecutive zeros have been replaced so as to suppress "0" continuity, and more particularly to a 1-bit error in a line. The present invention relates to a channel code decoding circuit capable of accurately detecting an error in a channel code received and received.

A code handled in the digital transmission system is an NRZ code having a narrow spectrum in the terminal equipment, a direct current component in the transmission line, and a bipolar code in which a timing component is easily extracted. However, if "0" continues for a long time in the original NRZ code, "0" continues for a long time even in the converted bipolar code, and it becomes difficult to extract the timing component. For this reason,
A code that restricts the number of consecutive "0" s is applied to a practical transmission path code.

For example, the HDB-3 code is a code adopted as a transmission path code in a digital transmission system of the CEPT system which is widely used mainly in Europe.
The outline of this code rule is as follows. (1) Four consecutive "0" patterns are detected and the fourth bit "0" is called a pulse ("1" or "-") which is called "violation pulse (hereinafter abbreviated as V pulse)".
1 "). This conversion pattern may be abbreviated as "000V". (2) If it is converted into a V pulse of "1" at a certain time, it is set to "-1" when it is converted into a V pulse next time. (3) The number of bipolar pulses (hereinafter abbreviated as B pulse; B pulse is also “1” or “−1”) existing between two V pulses must be an odd number. Therefore, when the B pulse is an even number, the first bit "0" of four consecutive "0" s
To B pulse. Also at this time, the 4th bit is converted into a V pulse. This conversion pattern may be abbreviated as "B00V".

As described above, the "0" sequence is suppressed and transmitted, but since the code itself has no error detection capability, the error rate cannot be known even if an error occurs in the transmission path. As long as the transmission system does not fail, it can be considered that the error is a random error. Therefore, it is usually possible to consider a 1-bit error. Therefore, when there is a 1-bit error, it is possible to detect it. Implementation of a -3 decoding circuit is desired. A similar function is also desired in a continuous zero-replacement code decoding circuit applied to other systems.

[0005]

2. Description of the Related Art FIG. 10 shows a conventional HDB-3 decoding circuit. In FIG. 10, 1 is a B pulse and V pulse detector, 2 is a shift register, 3 is a shift register,
5a is a pattern detection unit, 5b is a pattern detection unit, and 6
Is a code reproducing unit, and 10 is an error pulse generating unit.

The B-pulse and V-pulse detectors are supplied with a code obtained by separating the reception transmission path code into a positive-polarity pulse and a negative-polarity pulse. The B-pulse is output from one output terminal and the other output terminal is input. V pulse is output. These B pulse and V pulse are respectively input to a 4-bit shift register to undergo shift, and then "000V" and "B00V"
The pattern reproducing section inhibits the B pulse of the pattern which should be "B000" and reproduces 4 consecutive "0" patterns by this pattern. Also, the error pulse generator inhibits and outputs the pulse of the fourth bit of the pattern to be "000V". Therefore, when there is no error in the received code, four consecutive "0" s are output to both the decoding output and the error pulse output. When an error occurs, the decoded output contains an error pulse, and the error pulse output is "1" indicating an error.

However, the conventional HDB-3 decoding circuit is
Even if it is a 1-bit error, there is a problem that the error cannot be detected depending on how the error is generated, or the 1-bit error is evaluated as a 2-bit error, so that accurate detection cannot be performed.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a decoding circuit for a transmission line code capable of detecting all 1-bit errors by coping with such a problem.

[0009]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 1 is a B pulse and V pulse detection unit, 2 is a shift register, 3 is a shift register, 4 is a zero continuous detection unit, 5 is a conversion pattern detection unit, 6 is a code reproduction unit, and 7 is an invalid V pulse detection. , 8 is a temporary counting stop unit, and 9 is an OR circuit. In this configuration, the error detection function is characterized by an invalid V pulse detection unit that counts B pulses that enter between two V pulses that are temporally adjacent to each other, and a 4-bit shift register and the contents of the shift register. The zero continuous detection unit that detects "0" and the invalid V pulse detection unit output the error detection pulse, and the zero continuous detection unit detects four consecutive "0" and outputs the error detection pulse. It is a temporary counting stop unit that sometimes stops counting by the invalid V pulse detection unit until the next V pulse.

[0010]

The invalid V-pulse detector counts the B-pulses between the two V-pulses, and when the counting result is odd, inhibits the subsequent V-pulse and outputs nothing. If the counting result is an even number, the latter V pulse of the two V pulses is output to be an error detection pulse.

The zero continuity detecting section detects a pattern of all "0" s from the 4-bit shift register and the contents of the shift register. If the NRZ code has 4 consecutive "0" s, it is always converted into a pattern of "000V" or "B00V" according to the HDB-3 coding rule, so that the contents of the shift register and the shift register are all "0". Since this is not possible, an error can be detected based on the above detection result.

The temporary counting stop unit operates when the invalid V pulse detection unit outputs an error detection pulse and when the zero continuous detection unit outputs 4 times.
When a continuous "0" is detected and an error detection pulse is output, the counting of B pulses performed by the invalid V pulse detection unit is stopped until the next V pulse arrives. When four consecutive "0" s are detected, the B pulse count result may be an even number at the same time, and even when the invalid V pulse detection unit outputs an error detection pulse, four consecutive "0" s are simultaneously generated.
However, there is a possibility that a 1-bit error will be evaluated as a 2-bit error, but this can be prevented by temporarily stopping the counting of B pulses.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an embodiment of the invalid V pulse detector in the present invention. In FIG. 2, 71 is a selector and 72
Is an OR circuit, 73 is a flip-flop, and 74 is an AND circuit. In FIG. 2, basically, in the selector, the positive output and the negative output of the flip-flop are selected by the B pulse, the logical sum of the output of the selector and the V pulse is read by the flip-flop, and the output of the flip-flop is V The structure which controls the output of a pulse is shown. Since the output of the V pulse is stopped even when the temporary stop signal is generated, the temporary stop signal is also input to the OR circuit 74.

FIG. 3 is a time chart of the configuration of FIG.
The case where four B pulses come between two V pulses is shown by a thick line waveform. In the case of FIG. 3, when the positive output and the negative output of the flip-flop are selected by the B pulse in the selector and the logical sum of the output of the selector and the V pulse is read by the flip-flop, the output of the flip-flop is “FF The waveform is displayed as "Output". As a result, the latter V pulse of the two V pulses is logically ANDed with the FF output and output as an "invalid pulse". It is possible to detect an error because the even number of B pulses entering between V pulses is against the HDB-3 coding rule.

If the B pulse has a pulse shown by a broken line, the FF output also has a waveform like a broken line, and the subsequent V pulse is inhibited by the FF output. In this case, since the B pulse between V pulses is an odd number, there is no error assuming a 1-bit error, which indicates that there is no error.

FIG. 4 shows an embodiment of the zero continuity detecting unit according to the present invention, which is shown together with a shift register and a shift register. In FIG. 4, 2 is a shift register, 3
Is a shift register, 4 is a zero continuity detecting unit, 41 is a logical product circuit that logically inverts at the input, 42 is a flip-flop,
Reference numeral 43 is an AND circuit.

In the configuration of FIG. 4, "1" is output to the output of the AND circuit which is logically inverted by the input when all the bits of the shift register become "0", and this is input to the flip-flop and Q is input. ^{* The} output becomes "0" with a delay of 1 clock. Therefore, one pulse is generated from the output "1" of the AND circuit. If there is no error, all bits of the two shift registers cannot be "0", so that the output of the AND circuit 41 is always "0" and the AND circuit 43 outputs nothing. Therefore, the output of the one pulse can be used as the error detection pulse.

FIG. 5 shows an embodiment of the temporary counting stop unit in the present invention. In FIG. 5, 81 is an OR circuit, 82
Is a JK flip-flop. In the configuration of FIG.
The V pulse keeps the JK flip-flop in the set state, and when the invalid V pulse and four consecutive "0" s are detected, the JK flip-flop is toggled.

FIG. 6 is a time chart of the configuration of FIG. The output of the JK flip-flop is set to "1" by the first V pulse in the figure. In the figure, it is assumed that the second V pulse is an invalid V pulse, but the J-K flip-flop toggles by a single "invalid V pulse" pulse that is detected and output. It becomes "0".
Then, it keeps "0" until the next (third in the figure) V pulse comes. The output of the JK flip-flop is supplied to the invalid V pulse detection unit to stop the operation, so that a 1-bit error is not erroneously evaluated as a 2-bit error.

7 to 9 are time charts of the HDB-3 decoding circuit of the present invention. FIG. 7 is a time chart when there is no error, and FIG. 8 is a time chart when the V pulse of "000V" is wrong. FIG. 9 is a time chart when the B pulse of “B00V” is erroneous. In these figures, the original NRZ code is the same.

The "HDB-3 code" in FIG. 7 is obtained by converting the NRZ code into a bipolar code and then HDB-3 coding it. This "HDB-3 code" is decomposed into a B pulse and a V pulse and shifted by a shift register to obtain "B".
Pulse shift ”and“ V pulse shift ”. In the pattern after being shifted, patterns of "0000" and "000V" appear corresponding to "000V",
Corresponding to "B00V", "B000" and "0000"
Pattern appears. Therefore, when "000V" is detected, the original NRZ code is reproduced by inhibiting and outputting the pulse of the timing of the output of the shift register. At this time, no pulse is output to the error detection output.

FIG. 8 shows the operation when the first V pulse is erroneously set to "0". At this time, because the V pulse was wrong, "V pulse shift"
Since "0000V" appears where "000V" should appear, the four consecutive "0" detection units detect this and output an error pulse.

FIG. 9 shows the operation when the first bit of "B00V" is erroneously set to "0". Due to this error, "B000" that should appear corresponding to "B00V" becomes "0000", and the four consecutive "0" detection units detect this and output an error pulse.

Although only a few examples can be explained here, the fact that the present invention can accurately detect errors can be clarified by computer simulation.

[0025]

As described above, according to the present invention, an HDB-3 decoding circuit capable of accurately detecting a 1-bit error can be realized. Further, it is possible to provide a decoding circuit capable of detecting a 1-bit error even for zero consecutive substitution codes applied to different transmission systems.

[Brief description of drawings]

FIG. 1 is a principle of the present invention.

FIG. 2 shows an embodiment of an invalid V pulse detection unit.

FIG. 3 is a time chart of the configuration of FIG.

FIG. 4 is an embodiment of a zero continuity detecting unit.

FIG. 5 shows an embodiment of a temporary counting stop unit.

FIG. 6 is a time chart of the configuration of FIG.

FIG. 7 is a time chart of the HDB-3 decoding circuit of the present invention (when there is no error).

FIG. 8 is a time chart of the HDB-3 decoding circuit of the present invention (when the V pulse is erroneous).

FIG. 9 is a time chart of the HDB-3 decoding circuit of the present invention (when the B pulse is erroneous).

FIG. 10 is a conventional HDB-3 decoding circuit.

[Explanation of symbols]

 1 B pulse and V pulse detector. 2 shift register 3 shift register 4 zero continuous detection unit 5 conversion pattern detection unit 6 code reproduction unit 7 invalid V pulse detection unit 8 temporary counting stop unit 9 OR circuit

Claims (3)

[Claims] 1. A positive polarity data and a negative polarity data of a transmission path code are input to detect a bipolar pulse and a violation pulse from the transmission path code (1), and the bipolar pulse and the violation pulse are shifted. It shifts by the registers (2, 3), detects a specific pattern (5), and reverses the continuous zero-replacement code that has been code-converted to suppress a predetermined number of "0" continuous codes on the transmission side to "0" continuous codes. (6) In a circuit for decoding a transmission path code which reproduces a transmission code (6), an invalid violation pulse detection section (7) is provided, and a bipolar pulse that enters between two temporally adjacent violation pulses is generated. It is characterized in that it counts and outputs the later violation pulse of the two violation pulses as an error detection pulse depending on whether the counting result is even or odd. Decoding circuit sending passage code. 2. A bipolar pulse and a violation pulse are detected from the transmission line code by inputting data on the positive polarity side and data on the negative polarity side of the transmission line code, and shift the bipolar pulse and the violation pulse by a shift register. Then, the transmission line code which detects the specific pattern and reverse-converts the continuous zero-replacement code, which has been code-converted in order to suppress a predetermined number of "0" series on the transmission side, into a "0" continuous code. The decoding circuit for a transmission line code according to claim 1, further comprising: a zero continuation detecting section for detecting a predetermined number or more of zero continuations on the transmission line code and outputting the detected zero continuation error pulse. 3. The decoding circuit for a transmission path code according to claim 1, wherein a zero continuation detecting section and a temporary counting stop section are provided, and when the invalid violation pulse detecting section outputs an error detection pulse, and zero. When the continuity detection unit detects a predetermined number or more zero continuations on the transmission path code and outputs an error detection pulse, the time until the next violation pulse, the count for invalid violation pulse detection by the error detection pulse. A circuit for decoding a transmission line code, characterized in that