JPS61107817A - Binary code converting method - Google Patents

Abstract

PURPOSE:To prevent mis-detection of a synchronizing signal by setting a synchronizing signal pattern to a prescribed value in a 4-6 code conversion. CONSTITUTION:The reproduced 4-6 modulation data is identified by a data strobe circuit 1, a synchronizing signal detection circuit 2 latches sequentially data of N bits to detect whether or not the N bits are synchronizing signals. A synchronizing signal protection circuit 3 is provided with a detection window of several bits to latch a pulse outputted when the detection circuit 2 detects the synchronizing signal, thereby clearing a counter 4 to correct a 1/6 frequency division counter 4 generating a latch pulse to a 6-bit latch circuit 5 to a correct latch timing to a data stream where bit shift takes place due to dropout. The latch circuit 5 latches a 6-bit data by using a latch pulse generated by the 1/6 frequency division counter 4 and a 4-6 code conversion demodulation circuit 6 demodulates a 6-bit code word into a 4-bit data word in the same timing.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a synchronization signal pattern of a binary embossing conversion method,
In particular, it relates to a synchronization signal pattern for 4-6 code conversion, which is one of the binary code conversion methods.

[Background of the invention]

3PM (3Pos) is one of the conventional binary code conversion methods.
tion Modulation) published by Nikkei McGraw-Hill, December 11, 1978, "Nikkei Electronics" (December 11, 1978, P. 126-1)
64), pages 126 to 164, "Digital magnetic recording modulation/demodulation method j, etc.".
This converts a bit data word into a 6-bit code word, and this conversion table is shown in Table 1.

Table 1 In the connection between code words converted at this time, bit '1
When the number of bits 10' existing between ' and bit 11' is two, the polarity of the last two bits of the preceding code word and the first bit of the succeeding code word are inverted. According to this conversion rule, in the 3PM system, the minimum magnetization reversal interval 1111 Tnuyc = 15 'maximum magnetization reversal interval width T'' 6 T (where T is the data word bit cell interval).

Here, the synchronization signal of the 5PM system is the bit% of the codeword sequence.
11, as a pattern that never appears in the %01 array (hereinafter referred to as the code word data bit stream), as described in JP-A-57-154613,
10000000000001' and 12 consecutive 0s can be considered. Because it is 3PM method)
This is because the maximum number of consecutive values of , % o I is 11. However, if a signal containing this pattern is used as a synchronization signal pattern, it becomes T-45T, and! The disadvantages of IPM are: (1) self-clock recovery is difficult, (2) DC displacement is large, and (3) a wide transmission band is required. This is not preferable because the disadvantages such as the following will be further exacerbated.

Therefore, the synchronization signal pattern of the 5PM method is ' 00010
An example of 00000000001000' will be described. This is a beep) % o The maximum number of consecutive #s is 1
The number is 1 or less and satisfies the 5PM conversion rule. but,
This pattern is a pattern that appears in a position other than the synchronization signal on the data bitstream of the codeword. This situation will be explained with reference to FIG.

In Figure 2, A represents a bitstream of data words, -
is the name of the data word shown in Table 1. Further, B represents a pit stream of code words. Here, the data word series is arranged in the order of W2-Ws WoWl,
Each data word is converted according to the 3PM conversion rule to form a bit pattern such as the pit stream B of the code word in FIG. However, the pattern surrounded by S is the synchronization signal itself, and the synchronization signal will be erroneously detected here during demodulation, so the data words until the next synchronization signal is detected at the correct position will be erroneously detected. By demodulating the signal, the error rate worsens. In this way, when converting a data word into a code word, the synchronization signal pattern '0001000000000001000' occurs not only when the data words are arranged in W2 W5 WOL.

FIG. 3 shows the arrangement and appearance of data word sequences in which synchronization signal patterns are erroneously generated. In Figure 3, A is a pit stream of data words, B is a bit stream of code words, S is a synchronization signal pattern, and A' is a tree showing the arrangement of data word sequences when a synchronization signal pattern occurs erroneously. Table with diagram.

That's what I did. Let us now consider the probability that a synchronization signal pattern will occur erroneously. The 3-bit data word is Wo%W,
Among these, the probability that the data words are lined up as shown in Figure 3A' is the probability that the synchronization signal pattern will be generated erroneously, so the probability is p = -x -x -x -= - In other words, the synchronization signal pattern is '000100000'
If it is 0000001000', the probability that the synchronization signal will be erroneously detected during demodulation will be low, which is not preferable.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal pattern for binary encoding conversion that is not detected erroneously at positions other than the synchronization signal position on a data bit stream of a code word.

[Summary of the invention]

The present invention uses the worst pattern, which causes the greatest amount of code interference, among the code patterns that do not violate the code conversion rules and do not have the same pattern at any position on the bitstream including code-converted data and synchronization signals. By using a code pattern with a low pattern occurrence probability and low bit correlation as a synchronization signal pattern, erroneous detection of the synchronization signal is prevented.

[Embodiments of the invention]

The present invention relates to a synchronization signal pattern for a binary marking conversion method, and an embodiment of the present invention will be described below in connection with a 4-6 code conversion method, which is one of the binary marking conversion methods.

4-6 code conversion converts a 4-bit data word into a 6-bit code word, and the maximum number of consecutive bits 10' between bit q'1' and bit 11' is two, H
If RZ transform is performed, the DC component of the 6-bit code word becomes zero. This conversion table is shown in Table 2.

Margin Table 2 Below: Code word W5 shown in Table 2 + “6 r WD
+ WK + When code word W7 follows immediately after WF, there are three consecutive bits 10' between bit 11# and bit 11', so the previous code word (W5r"F +WDyWE+
W? ), and in order to cancel the resulting DC component, the trailing code word (w7) is inverted to 11'.
is replaced with the '100101' pattern.

By combining the 4-6 code conversion with the NRZr conversion, the maximum magnetization reversal interval FM Tmax - 3T1 the minimum magnetization reversal interval Tm1fL = T (where T is the bit cell interval of the code word), and the maximum magnetization reversal interval is 2 words ( The DC component is zero within the code word (12 bits).

Next, the block diagram of the demodulation circuit of the 4-6 code conversion method is shown in the fourth section.
As shown in the figure. In FIG. 4, 1 is a data strobe circuit;
2 is a synchronous signal detection circuit, 3 is a synchronous signal protection circuit, 4 is 6
5 is a 6-bit latch circuit, 6 is a 4-6 code conversion demodulation circuit, and 7 is a 4-bit shift register. The 4-6 modulated data reproduced in FIG. Detect whether a pit is a sync signal. The synchronization signal protection circuit 3 has a detection window of several bits and latches the pulse output when the synchronization signal is detected by the synchronization signal detection circuit 2. The counter 4 is cleared in order to correct the 6-frequency divider counter 4, which generates the latch pulse of the bit latch circuit 5, to the correct latch timing. Generated by 6 frequency division counter 4.

The generated latch pulse causes the latch circuit 6 to latch 6-bit data, and at the same timing, the 4-6 code conversion demodulation circuit 6 demodulates the 6-bit code word shown in Table 2 into a 4-bit data word. Further, the demodulated 4-bit data is loaded into the 4-pit shift register 7, shifted at the timing of the clock OK2, and the demodulated data is output from the output terminal.

Here, the synchronization signal pattern is set to 12 bits, and '110
An example of 011100111' is shown in Figure 5 A) to D)
This is explained by: This 12-bit pattern is bit%
The maximum number of consecutive bits %01 between bit 11 and bit 11' is 2, and the MRZ conversion of this pattern in Figure 5B) shows that the sum of positive pulse widths and the sum of negative pulse widths are Similarly, the DC displacement shown by (0) in the figure converges to 0, so the DC component is zero, and the 4-6 sign conversion rule is satisfied. Furthermore, this 12-bit pattern is a pattern that will never appear anywhere other than the position of the synchronization signal, no matter which 12-bit pattern is searched on the data bit stream of the code word containing the synchronization signal. In addition, this synchronization signal pattern has the greatest influence of code amount interference due to the connection of code words before and after it, and is the worst pattern that is likely to cause bit errors, that is, the interval of magnetization reversal is T-T1n.
There is no case where it becomes LyuT7XIJ. This is Figure 5 (D)
As shown in Figure 2, in order to form the 5T-T-5T pattern, which is the worst pattern in the 4-6 code conversion method, the last 3 bits of the code word immediately before the synchronization signal pattern must be '1o'.
o', such codewords are shown in Table 2.
This is because it does not exist in

In addition, Figures 5 (A) to (G) show 11 synchronization signal patterns.
In another example of 00111110011', E) represents a data bit stream consisting of a synchronization signal and code words before and after it. Here, the synchronization signal pattern is s Tm
ax≦3, and (F) represents a DC displacement in this data bit stream, indicating that this synchronization signal pattern does not have a DC component. Both of these satisfy the conversion rules of the 4-6 code conversion system. So the synchronization signal pattern is '1001111100
11', the case where the worst pattern is formed is shown in Figure 5G), when the last 4 bits of the code word immediately before the synchronization signal are the '1001' pattern, or when the code word immediately after the synchronization signal The worst pattern, 5T-T-5T, is formed when the first three bits of are 1001'. This means that the code word immediately before the synchronization signal is data w7 shown in Table 2.
．． When wB, the worst pattern is formed and the probability of that event occurring is earth. Furthermore, the worst pattern is also formed when the code word immediately after the synchronization signal is W7. Since the probability of this event occurring is high, it is worst when the synchronization signal pattern is '100111110011'.

The probability that the pattern occurs is p=2 1. =3W
16 16 16.

Next, consider the bit correlation of this synchronization signal pattern. Here, the idea of bit correlation includes the synchronization signal pattern,
In the 12-bit code word data stream consisting of the previous and subsequent code lengths, several bits are erroneous due to synchronization signal dropout, etc., and as a result, the probability that the same pattern as the synchronization signal pattern will occur again at a position other than the synchronization signal position is calculated.
This probability represents the strength of bit correlation in the synchronization signal pattern.

In other words, a strong bit correlation indicates that there is a high probability of erroneously detecting a synchronization signal due to a pit error. Figure 6 shows the synchronization signal pattern '11001110
011' is a diagram showing how a synchronization signal pattern appears at a position other than the synchronization signal position due to bit correlation. In FIG. 6, M1 to M11. L1~I,
N, BS represents the data bit stream of the codeword, BS indicates the correct position of the synchronization signal, and M
1~M11°L1~], +11 indicates a case where the synchronization signal pattern appears at a position other than the correct position of the synchronization signal.

Here, in the area of the synchronization signal pattern, a bit enclosed in parentheses represents a state in which an error has occurred in the bit of the synchronization signal at this position. Also, symbols A, 3. In the X and Y regions, * represents an undefined state that can be either %11 or 101. Therefore, for example, the probability that the event (L4) will occur is determined.

Now, if the pit error rate is 6, the probability that any one bit will cause an error is 8, and in the case of (L4),!
97. S? , 812 causes an error is πi@5, and the first 4 bits of code word X, (3:1.31
2, JIB, Je4) is '0111' in Table 2. Since there are only two w3,
The probability of taking this code word is on the left, and the probability that event (L4) will eventually occur is PI,4. Similarly, Table 3 shows the probability that events L1 to TJ11 and M1 to M11 will occur.

Table 3 Therefore, the bit correlation of this synchronization signal pattern is as follows. Here, if e < 1, it can be similar, and the smaller this value is, the more suitable it is for the synchronization signal pattern. Table 4 shows an example of the worst pattern occurrence probability and bit correlation obtained using the above method for other synchronization signal patterns in the 4-6 code conversion system.

Margin Table 4 Below, FIG. 1 shows an example of a synchronization signal detection circuit for an example in which the same signal pattern of the 4-6 code conversion system is '110011100111'.

In FIG. 1, 201 is a 12-pit shift register, 2
02, 203, 204, 205 are inverters, 2
08 is a 12-person AND gate. Here, the modulated data that has been subjected to 4-6 code conversion is shifted bit by bit into the shift register 201 by clock aK, and the shifted 12-bit data stream is converted into the synchronization signal pattern '
10011100111', bit 10' of this pattern is changed to 11 by inverters 202-205.
', AND game) All 208 inputs are 11
'. Only at this time, AND gate 208 outputs a positive pulse.

FIG. 7 is a diagram showing another embodiment of the synchronization signal detection circuit according to the present invention. In FIG. 7, 211 is a 6-bit shift register, and 61 is the first half 6 of the 12-bit synchronization signal.
A bit pattern matching circuit, 62 is a subsequent 6-bit pattern matching circuit, 33 is a hexadecimal or divide-by-6 counter, 2
22 is a two-person AND gate. In the figure, the reproduced modulation data is shifted one pit at a time to the shift register 211 by the clock, and at this time, the contents of the 6 bits of the shift register 211 are the first half 6 bits or the second half 6 bits of the synchronization signal shown in Table 4. Matching circuits 31 and 32 determine whether or not they match. Here, if the first six bits match, a positive pulse is output from the output terminal s1. If the latter six bits match, a positive pulse is output from the output terminal S2. In this circuit, when a synchronization signal pattern is manually input as a reproduced signal, a positive pulse is first output from the coincidence circuit 61,
After this signal resets the hexadecimal counter 53, a positive pulse is output from the output O after counting clocks for 6 hits. At this point, the contents of the shift register 211 are the contents of the latter six bits of the synchronization signal, so the coincidence circuit 32
A positive pulse is output from the output terminal S2. Therefore, the output obtained by ANDing sl and 82 is MO, and when MO outputs a positive pulse, it indicates that a 12-bit synchronization signal has been detected. Therefore, in this embodiment, when detecting a 12-bit synchronization signal, the circuit can be simplified using a 6-bit shift register and a simple hexadecimal counter.

Next, according to the present invention, the synchronization signal pattern is changed to 111j100.
111011', an embodiment of the synchronous signal detection circuit will be described with reference to FIG. i and FIG. 9. In this example, the synchronization signal pattern '111100111011
' is divided into the first 6 bits and the last 6 bits and compared with the code word of 4-6 code conversion, each pattern is different by at least one pit, that is, this synchronization signal pattern is the same as that of 4-6 code conversion. This is an example of an implementation method that utilizes the feature that the distance between codes and a code word is 2.

In FIG. 8, the modulation data is shifted one pit at a time to the 12-bit register 250 by the clock OK1, and this data is transferred to the synchronizing signal pattern 1111100111011.
'When bit '1' is 4 people' AND
Input to gate 220.5 human power AND gate 23o,
Bit% o J is inverter 206, 207°20
By inputting to 8, 3-person AND game) 23
2. The two-man-powered AND gate 231 both generate positive pulses, and the two-man-powered OR gate 234 and the two-man-powered AND gate 235 generate pulses that detect synchronization signals.

If one pit of the 12-bit synchronization signal pattern causes an error, the AND gate 232 or 231 is activated depending on whether the error data is in the first 6 bits or the last 6 bits of the 12-bit synchronization signal pattern. By outputting a positive pulse from one side, the synchronization signal is determined.
Synchronous signal detection from R gate 234.

Outputs the output pulse. In FIG. 9, 250 is a 12-pit shift register, 252 is a ROM or PLA, and an example of the input/output functions is shown in Table 5.

However, in Table 5, * represents indefinite.

Table 5 In Figure 9, the modulation data is clocked by OK1.
Shifted one bit at a time to the 12-bit shift register 250, and click OK every time 12 bits are shifted.
2, the data in the shift register 250 is latched into the 12-bit latch circuit 251. By inputting this data to a ROM or PLA with an input/output relationship as shown in Table 5, a synchronization signal pattern with an error of 1 bit or less is determined, and a synchronization signal detection pulse is output from the output terminal SO or MO. Output 0 FIG. 10 is a block diagram showing an embodiment of a 4-6 code conversion demodulation circuit according to the present invention. In the same figure, 211 is 6
Bit shift register 35 is 80M or px, h, 5
7.58 is a 4-bit latch, and 36 is a synchronization signal detection and clock generation circuit. In FIG. 10, the reproduced signal, which has been identified and shaped by the data strobe, is shifted into the shift register 211 one bit at a time. This data is demodulated by the ROM or PLA circuit 35 as shown in Table 2 every time it is shifted one bit. D1-D4
The signal is output to the latch circuit 37 or 38 and latched. The ROM (PI, A) 55 also defoods the first half, second half, and half 6-bit patterns of the synchronization signal shown in Table 4, and when these 6-bit patterns match, the output terminal 81. By outputting a positive pulse from S2, a synchronization signal is detected by the clock generation circuit 36, and at the same time, latch pulses are alternately outputted to the latch circuits 37 and 38 every 0K16 clock pits according to the synchronized timing. According to this embodiment, since the 12-bit synchronization signal shown in Table 4 is a pattern that does not exist in the code word of 4-6 code conversion, it is stored in the demodulation ROM (PLA
) and a synchronization signal number circuit can be shared. [Effects of the Invention] If the synchronization signal detection circuit using the synchronization signal pattern according to the present invention is adopted, digital recording and reproduction using the 4-6 code conversion method can be performed. The device can do the following:

(1) The 4-6 code conversion rule is not violated. That is, it has no DC component and can have a minimum inversion interval of 0.67T (where T is the data bit cell interval) and a maximum inversion interval of 2T.

(2) The synchronization signal pattern can be a pattern that never appears in any position other than the synchronization signal at any position on the data bit stream of the code word containing the synchronization signal.

(3) Among the patterns that satisfy (1) and (2) above, the probability of occurrence of the worst pattern with the maximum peak shift is the minimum, and the probability of becoming the same as the synchronization signal pattern due to several bit errors, that is, the bit correlation is the minimum. The pattern can be a synchronization signal.

(4) Among the 12-bit synchronization signal patterns that satisfy (1) and (2) above, a 1-bit error occurs by adopting a pattern in which the code distance from the code word in units of 6 bits is 2 for the synchronization signal. It can be detected as a synchronization signal even if

(5) The synchronization signal can have a length that is an integral multiple of a 6-bit code word, and if each word is made up of 6 bits, each word will not be the same as the code word after 4-6 conversion. It is possible to perform pattern detection every 6 bits (1 word), and the scale of the synchronization signal detection circuit can be reduced.

From the above, the present invention has the effect of improving the error rate by making maximum use of the effect of 4-6 code conversion and reducing the number of erroneous detections of synchronization signals. Moreover, this effect can be achieved by a simple and small-scale synchronous signal detection circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of detecting a synchronization signal pattern according to the present invention, the second part is a diagram showing how a synchronization signal is erroneously detected in the 3PM system, and Figure 3 is a circuit diagram showing how a synchronization signal is detected incorrectly in the 3PM system. FIG. 4 is a block diagram showing an example of a demodulation circuit for the 4-6 code conversion method. FIG. 5 is a synchronization signal for the 4-6 code conversion method. A diagram showing how the worst pattern occurs around the pattern, FIG. 6 is a diagram showing the bit correlation in the synchronization signal pattern of the 4-6 code conversion method, and FIG. 7 is an example of detecting the synchronization signal pattern according to the present invention. FIG. 8 and FIG. 9 are circuit diagrams showing other embodiments of detecting a synchronization signal pattern according to the present invention, and FIG. 10 is a block diagram showing an embodiment of a demodulation circuit according to the present invention. . DESCRIPTION OF SYMBOLS 1... Data strobe circuit, 2... Synchronous signal detection circuit, 3... Synchronous signal protection circuit, 4... 6 frequency division counter, 5... 6-bit latch circuit, 6... 4- 6 code conversion demodulation circuit, 7... 4-bit shift register, 201... 12-bit shift register, 202.20
5,204,205,206,207,208,209
...Inverter, 211...6-bit shift register, 212.213...6-bit latch circuit, 25
0...12-bit shift register, 208...12
Human powered AND gate, 220.221...4 human powered AND gate, 216...
・6-person AND gate, 2!11.255...2-person AND gate, 230・
...5-manpower AND gate, 254...2-manpower OR gate, 252...12-manpower ROM or PLA. 31... Matching circuit for the first half 6-bit pattern of the 12-bit synchronization signal, 32... Matching circuit for the latter half 6-bit pattern of the 12-bit synchronization signal, 222... Two-man power AND gate, 33... Hexadecimal counter , 35... RO for demodulation and synchronization signal pattern decoding
M or PI, A. 36... Synchronous signal detection and clock generation circuit, 37
．． 58...4-bit latch circuit. Representative Patent Attorney Akio Takahashi Diagram 1 Synchronous communication is possible. Condolences Recruitment Figure 3 ¥7 Figure Sorry.

Claims (1)

[Claims] 1. Divide a continuous binary data series into 4-bit units,
In the 4-6 code conversion that converts a 4-bit data word into a 6-bit code word that contains at most two non-inverted points between adjacent inverted bits and has zero cumulative charge within each code word. , 4-6 A binary code conversion method characterized in that a code pattern that does not exist in a continuous bit sequence of 6-bit code words converted to a 4-6 code is used as a synchronization signal pattern. 2. In claim 1, the synchronizing signal pattern is a code pattern in which the ratio of the sum of positive pulse widths to the sum of negative pulse widths is 1:1 after HRZI modulation. A binary code conversion method characterized by the following. 3. In claim 2, the code length of the synchronization signal pattern is 12 bits, and the following code patterns 110011100111, 111100111001
, 111001110011, 10010110110
1, 100111110011, 1001110011
11, 111001110011, 011001110
A binary code conversion method characterized in that one code pattern among 011 is used as a synchronization signal pattern. 4. Claim 2, characterized in that the synchronization signal pattern is a code pattern that reduces the probability that the worst code pattern with the maximum interference between adjacent codes will appear among the synchronization signal patterns. Binary code conversion method. 5. In claim 2, the synchronization signal pattern is identical to the synchronization signal pattern due to one or more 1-bit code errors in a code sequence consisting of a synchronization signal and code patterns connected before and after the synchronization signal pattern. A binary code conversion method characterized in that a synchronization signal is a code pattern that reduces the probability that the pattern will appear. 6. In claim 2, in the synchronization signal pattern, two or more contradictory codes exist between the synchronization signal pattern and a code pattern having a code length equal to the synchronization signal pattern length (synchronization A binary code conversion method characterized in that a code pattern in which the inter-code distance between a signal pattern and a code pattern formed by a combination of code words after 4-6 conversion is 2 or more is used as a synchronization signal pattern. 2. The binary code conversion method according to claim 6, characterized in that the circuit for detecting the synchronization signal pattern includes a circuit for determining the synchronization signal with a code length smaller than the synchronization signal pattern length. .