JPS59231956A - Binary code converting system - Google Patents

Abstract

PURPOSE:To widen the width of a detecting window by corresponding a data word to a code where a DC component in a word is zero when a data word is converted into the code word and replacing the code into a specific bit pattern when zero is consecutive between the 1st and the 2nd code words. CONSTITUTION:A consecutive binary data series is split in the unit of 4-bit and the data word in 4-bit is converted into a code word in 6-bit. This converting system is provided with 4-bit shift registers 1, 2, an ROM 3 with 4-bit input and 6-bit output and a discriminating circuit 4. This discriminating circuit 4 discriminates a pattern where specific inputs are consecutive just after the data word input. Further, an output signal of the ROM 3 is added to a multiplexer 6 so as to be shifted into a 6-bit shift register 10 via shift registers 7, 8. Then the conversion into the code word is conducted so that the DC component in the word is zero and when Os are consecutive between the 1st and the 2nd code words, 12-bit is replaced into the code word of a specific 12-bit pattern.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a binary code conversion method applied to transmitting digital signals such as in magnetic recording and reproducing devices [Background of the Invention] AI FM is known as one of them. This means that data bit 11' is inverted at the center of the bit, and when bits ``0'' are consecutive, they are inverted at the boundary between bit '01 and bit 'OI'.

This situation is shown in FIG. Here, the data bit interval is T
Then, the maximum magnetization reversal interval Tmax of MFM modulation =
2TI minimum magnetization reversal interval Tm1n=T, detection window width 7tu
=0.57'.

Here, in order to estimate the DC component of MFM modulation, +1. For negative minimum pulse width T -
1, and considering the cumulative charge calculated by assuming a charge of +2 for a pulse width of 2T, which is twice that, M
In the case of FH, when the data continues in the pattern of 'NO', as shown from point A to point 0 in Figure 1, +
Charges are accumulated one by one, and the frequency spectrum of the 1MFM recording current waveform has a DC component. Generally, in magnetic recording and reproduction, the recording current waveform is transmitted through an AC coupling element, so the recording current waveform having a DC component is distorted, and during reproduction, the DC component lost due to AC coupling cannot be reproduced.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a binary pulse modulation method which has a wide detection window and does not have a free current component in the frequency spectrum of the recording current waveform.

[Summary of the invention]

4) When performing group coding to convert a 6-bit data word into a 6-bit code word, the present invention associates codes such that the DC component in the 6-bit word is 0, and converts the converted first When there are 5 or more 'oI's in succession between a code word and a second code word that follows it, replace the 12 bits of the first code word and the second code word with a code word with a specific 12-bit pattern.W be.

[Embodiments of the invention]

The present invention converts a 4-bit data word into a 6-bit code word from 64 types of code word patterns.

Maximum of 2 consecutive hit 10's or less, 6 pinots 1
A code word in which the DC component in the q-code is 0 corresponds to a 4-bit data word. An example of the conversion is shown in Fig. 2 (however, in order to estimate the DC component in the code word, +1 for the positive minimum pulse width 2/3T, and +1 for the negative minimum pulse width 2/3T).
15 Tvc pair (accumulated on the assumption that the charge is +3 for a pulse @2T that is 3 times the 7 and -1 degree). However, if the second codeword '001001' immediately follows the first codeword whose last bit is '0', then the pinto%oI
This results in five consecutive pulses, which violates the conversion rule and increases the pulse width.

As shown in FIG. 6, for example, the first code word '0100
10' Second code word 'ooioo+' after Noiii
If continuous <, there is no DC component but non-inverted pitch) %
There are 6 oIs in a row. Therefore, '1+1110111001' shown in FIG. 5 is assigned as a code word to be replaced. This can be easily identified because the DC component within 12 bits is 0 and it is a pattern that has not existed in the past.

Figure 5 shows the cumulative charge of the previous 6 bits of the code word to be replaced by +2.
．． This is an example of a pattern in which the cumulative charge of the last 6 bits is -2 and the cumulative charge is 0 within 9.12 hits. The code word to be replaced has a maximum of 3 or more consecutive bits 10' and 1
It is sufficient to allocate a code word such that the accumulated charge within two pits is zero.

FIG. 4 is an example of another code conversion according to the present invention.
In the case of a special pattern in which three or more bits 10' are consecutive between the code word and the second code word that is subsequently converted,
This is an example in which a code word to be replaced is generated using the conversion rule shown below.

In the case of a special pattern with three consecutive ``0''s, the conversion rule is (1) invert the last bit 10' of the first code word to Y;

(11) Replace the subsequent second code word 'oo+oo+' pattern with the '100101' pattern.

This situation is shown in FIG. Figure 4: 0 and the last bit 10'
Flip to Y. However, this reversal results in accumulation of +2 cumulative charges. Therefore, as shown in FIG. 4(h), instead of the pattern '001001', a pattern '100101' which cancels out the accumulated +2 charge is created.
By corresponding as a backup code, up to 12
The accumulated charge within the bit 2 code word is set to 0, and the DC component can be completely removed from the modulated signal. Note that in the present invention, '100101' was used as the preliminary code.

Other patterns in which the cumulative charge is 2 and bits 10' are consecutive at most 2 or less, such as '10011
1', '111001';'1ONO1',
'010'011' can also be used as a backup code. Figure 4(C) is '+0011+'
This is an example using as a preliminary code.

FIG. 5 shows an example of the configuration of this modulation circuit.

In Figure 5, 1.2 is a 4-bit shift register, 6
is a ROM with 4 pin input and 6 pin output.

4 is a discrimination circuit, 5 is a latch, 6 is a multiplexer, 7
, 10 represents a 6-bit shift register, 8 represents a 1-bit shift register, and 9 represents an exclusive OR. Here, the discrimination circuit 4 inputs the data word input '''5# in FIG.
, 16M, %,, #, %f, %, /,
17' is immediately followed by 17', and if it is not one of these special patterns, the output signal of ROM5 passes through shift register 7.8 to shift register 0.
and becomes the modulated output. The contents of the ROM 5 are written so that a 6-bit code word is output in response to a 4-bit data word input from 0 to F shown in FIG. Figure 6 shows the time chart of the warping operation when the above-mentioned special turn occurs.Here, register 2 contains %5#, @, #, %11.
, t4# means that the data word input in Figure 2 is 4.
The 1 discrimination circuit 4 generates a pulse when eight pits of the special pattern are aligned in the shift registers 1 and 2.

At this time, the multiplex key 6 selects the preliminary code '100101' as the output of the data language ability %, I, loads it into the register 7, and outputs the final code word '0' which is delayed by the register 8. 4 output pulses
cllLsive Operate with OR9 and invert to pit 1'. This is loaded into the register 10 and converted.

FIG. 7 shows another embodiment of the present invention. In FIG. 7, the same symbols as in FIG. 5 have the same functions.

20.21.22 is 2 person Exc1wive OR, 2
5* 24, 25 are inverters, 26 is 3-man power A N
Show D. This will be explained below using the diagram. Data is sequentially shifted to register 1, and 6 ROMs are stored in 4-bit units.
is converted into a 6-bit code word and loaded into register 7. This signal is sequentially shifted to register 8 and Ex
- Obtain modulated output from OR9. Here, the last codeword of the first codeword is ``0'' and the second codeword is %ooi oa
t', when the last bit %ON of the first codeword is shifted into register 8, the second codeword is transferred to ROM5.
is output from. At this time, six consecutive pits 0'' are K, and the AND gate 26 becomes H' due to the outputs of the outputs 25, 24, and 25.
The output of shift register 8 is inverted by the output of ROM 5, and the 1st, 5th, and 4th bits of the output of ROM 5 are inverted by Ex-OR 20, 21, and 22, respectively, and '100101' is loaded into register 7. Ru. As a result, the last bit of the first code word is inverted, and the second code word that follows it is inverted.
The codeword is loaded into the shift register 7 as a '100101' pattern.

〔Effect of the invention〕

According to the present invention, the frequency spectrum of the recording current waveform, which is the signal after modulation, does not include a DC component. Also, the maximum magnetization reversal interval Tmαx=27. Minimum magnetic 7'mar conversion reversal interval Tm number n -15T + /Twin
= 5.0 Te, and MF for detection window width 7w
In contrast to H's 7w = 0.5T, in this modulation method Tw =
It becomes 0.67 T, and it is possible to widen it by about 6096 T.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing MFMFM modulation and accumulated charge, FIG. 2 is a diagram showing an example of conversion according to the present invention and its accumulated charge, and FIG. 3 is a conversion table for a special pattern according to the present invention. Diagram showing an example. FIG. 4 is a diagram showing an example of the conversion rule and its accumulated charge in the case of a special pattern according to the present invention, FIG. 5 is a block diagram showing one embodiment of the modulation circuit according to the present invention, and FIG.
FIG. 7 is a time chart diagram showing the operation of the block shown in the figure in a special pattern, and FIG. 7 is a block diagram showing another embodiment of the present invention. 1.2...4 pit shift register. 6...4-bit input, 6-bit output ROM. 4...Discrimination circuit. 5...Latch. 6... Multiplexer 1 7, 10... 6-bit shift register. 8...1 bit latch. 9-...Exclu, sivtOR0 4th round (of (g)CC) (δOl Procedural amendment (spontaneous) Indication of case 1982 Patent application No. 105881 Title of invention 2-cage code conversion system Amendment person times Difficulties with patent applicant name (510) 11 Hitachi Co., Ltd.
・Subject of correction: A simple Ili of Seimei 9 drawing of IJ11 #1 Gypsum Illusion! Ming's ball and drawings. Contents of amendment t Specification 11: The following sentence is added between page 9, line 14 and column 15. Figure 7M8 shows an example of another conversion using this fiillHc. In this conversion example, 64 6-bit code word patterns have consecutive bits of 0 degrees or two or less, and the DC component after the yRzi change is zero. Here, the last bit of the code word is °0° is A2B.
, 6, 7.1), F. If this code word is followed by 14 codes, there will be three consecutive '01's at the boundary. The end of the broken code word "01" is reversed to 111, and the string (
/164 code from "001001' to preliminary code"
1ooioi'rc* is to be replaced. In this way, the DC component generated by inverting the last bit in the code word at the beginning of the failure is compensated for by the backup code on shoulder 4. As a result, usually the DC component for each No. It is a modulation method that operates so that the DC component becomes zero in units of two code words only in the above case.
A demodulation circuit is shown. Figure 9 shows 1. n[, 40 is a latch circuit for input 4-bit latch, 41 is a gate circuit for detecting IC,
42, 45 are latch circuits, 44 are gate circuits, 45
46 is a gate circuit for bit control, and 47 is an output data latch circuit. Further, in FIG. 10, 50 is a 6-bit code word latch circuit, and 51 is a pLA of ANI)-OR configuration.
, 52 is a gate circuit for 41i-different code detection. The circuit production for modulation and demodulation will be explained below. In Figure 9, the 4-bit data "'C" is stored in the latch 40. At the same time, the gate 41 outputs * whether this data is 14m or not, and it is stored in the latch 42. - The latch 43 is connected to the previous 1C It is detected whether the end of the converted data is 001 or not and stored.The output of the latch 40 is manually inputted to the Q-factor pLA45, and the output of the PLA45 is a 6-bit code according to the conversion rule shown in FIG. If the code following 0 is 141, the output of gate 41 is 11"
Then, forcing the J9LSB bit to gate 46 to 11°
Make it. '! If A5, 6, 7, D, FIG, tFAZ
PLA45ノLSB 1:'ytokL'0'jknee f, C, latch 45 [Once stored. Next 1
When the data of 41 is <1), the output of gate 44 becomes 111 and enters gate 46. Of this result data 141, the MSB, 4th bit is 0.
11, 5th bit & ma @ 0" and rL retarder 4"
is converted into a preliminary code. -1 demodulation, 6-bit data is input to the rear leg circuit shown in FIG. Here comes the bit. Chip 1s@,'s” 97m, “D”, I
Other than F1, the race is always 81", and the data is 151,
@6°, -m7°. Even in °D" and "Fo, if the next data is m4°, it becomes 11I. From now on, we can rearrange the data using only 5 bits excluding the last bit.60 Also, as shown in Figure 8, when the 2nd and 5th bits are both m1°, the last bit of the data is 111, then 2 bits. It is possible to demodulate the last bit of the data by using the yal-gate 52 to demodulate the last bit of the data. The shallow 93 bits can be demodulated by pLA51. As mentioned above, it is possible to reduce the circuit scale of the variable m circuit for binary decoding by using the conversion rule shown in FIG. ” 2 Ming #I Zeng, page 10 A, “It is a block.” on line 14 is 1-Glock diagram, @8 figure is a diagram showing another example of conversion by unexploded tn,
Changes in the Law of Conversion of Factors - Circuit Diagram, Figure 10 is a circuit diagram. MTiE to '. 3. Add Figures 8, @9, and ■10 as shown in the attached sheet. More than $ ■ Figure q

Claims (1)

[Claims] 1. Divide a continuous binary data series into units of 4 and Z bits, and convert 4-bit data words into 6-bit code words. 2.
In the value conversion method, a 6-bit codeword includes at most 2 non-inverted pits between adjacent inverted pits,
And the ratio of the sum of the positive interval width and the negative interval width is 111. If there are 3 or more non-inverted bits consecutively between the converted first code word and the subsequently converted second code word, the positive difference between the first code word and the second code word is The ratio of the sum of the interval width and the negative interval width is 1:1, and there are at most 2 non-inverted bits between adjacent inverted bits.
A binary code conversion method characterized by replacement with a bit code word. 2. In the binary code conversion method 2 according to claim 1, the non-inverted bits are 3 bits between the converted first code word and the subsequently converted second code word. If the above sequence occurs, the last bit of the first code word is set as an inverted bit. A binary encoding conversion method characterized in that the ratio of the sum of the positive interval width and the negative interval width of the second code word is replaced with a 6-bit code word of which the ratio is 112.