JP2586073B2 - Frame synchronization method - Google Patents

Description

BACKGROUND OF THE INVENTION [Field of the Industrial] This invention, the frame synchronization method, a frame synchronization method for digital signals modulated by a particular M ² code [M Square code].

[Summary of the Invention]

In the present invention, a unique sync pattern never formed from M ² code modulation rule at an arbitrary position of the M ² encoding prior to digital signal provided, the beginning of this unique sync pattern, the end of the DSV after the zero, and is configured to be modulated by M ² code.

Therefore, the sync pattern can be easily and reliably detected, and erroneous detection of the sync pattern can be prevented. As a result, the occurrence of a synchronization shift and a synchronization error can be prevented. Further, frame synchronization can be accurately and stably achieved, and digital signals can be reproduced faithfully. At the same time, since the detection of the sync pattern becomes easy and reliable,
The shortest sync pattern can be formed with the minimum number of bits, and the redundancy for frame synchronization is not increased. Furthermore,
The DSV of the digital signal following the sync pattern can be kept within ± 1.5, and a DC-free state can be guaranteed.

[Conventional technology]

The modulation method of the digital signal have been proposed various types conventionally, there are M ² code that is disclosed in JP 52-114206 in one of them. The M ² code, the mirror code as the basis, can remove the DC component of the digital modulated signal is a code called DC-free.

M ² code, and the length of Pittoseru is T, the minimum inversion interval T _min = T, the detection window width T _w = 1 / 2T, the maximum inversion interval T _MAX = 3
This is a self-clocking code of T, ( _TMAX / _Tmin = 3), and is a reasonable code as long as the data rate is not so high.

By the way, when reproducing a digital signal, accurate frame synchronization must be achieved. For this purpose, it is necessary to provide a sync pattern that can be clearly distinguished from data in the digital signal. For example, in the 8-10 modulation method used in RDAT, it is possible to form a unique (not occurring in a data stream) sync pattern. However, in the M ² code described above, the unique sync pattern is not to be defined in the coded digital signal.

Therefore, conventionally, the data signal before ² encoding M, in the form of NRZ, select the pattern present in one probability in the data, is inserted into a digital signal, has been subjected to M ² code modulation.

[Problems to be solved by the invention]

As described above, since a specific data pattern is inserted into a digital signal as a sync pattern, this sync pattern cannot be unique, and the same pattern as the sync pattern is also included in the data block with a certain probability. There was a problem that it occurred.

For this reason, the above-mentioned data may be erroneously detected as a sync pattern. As a result, a synchronization shift and a synchronization error occur, making it difficult to accurately obtain frame synchronization.
There is a problem that it becomes difficult to accurately reproduce the digital signal.

Further, in the above-described conventional technique, the data length of the sync pattern generally tends to be long in order to reduce the probability of false detection, and there is a problem that redundancy for frame synchronization is increased. Improvement was desired.

Therefore, an object of the present invention is to accurately and stably achieve frame synchronization and to form a shortest sync pattern,
It is still another object of the present invention to provide a frame synchronization method which guarantees that a sync pattern and subsequent digital signals are DC-free.

[Means for solving the problem]

In the present invention, a sync pattern satisfying the following requirements (a) to (c) is provided at an arbitrary position of the M ² encoding before digital signal, modulated by M ² code.

(A) The sync pattern is a sync data pattern having a predetermined number of bits, “0” data provided before the sync data pattern, and between the “0” data and the sync data pattern. Start DS
At least one control bit whose polarity is controlled to be inverted according to the DSV at the end of "0" data so that V is set to zero.

(B) the sync data pattern signal transition interval after receiving the M ² encoding is 2.5T (where
T is the length of the bit cell of the signal before coding, and is the reciprocal of the data rate. ) And a data pattern with a signal transition interval of 2.5T, and the signal transition interval is
A data pattern that is one of 2T, 2.5T, 3T,
Data patterns which can be a unique is provided at least one set in M ² code of the data stream without a set between.

(C) At the end of the sync data pattern, a fixed data pattern for setting the end DSV of the sync data pattern to zero is provided.

Further, in the present invention, a sync pattern satisfying the following requirements (a) to (c) is provided at an arbitrary position of the M ² encoding before digital signal, modulated by M ² code.

(A) The sync pattern is a sync data pattern consisting of a predetermined number of bits, “0” data provided before the sync data pattern, and between the “0” data and the sync data pattern. DSV
Is made up of at least one control bit whose polarity is controlled to be inverted according to the DSV at the end of "0" data so as to make zero.

(B) the sync data pattern signal transition interval after receiving the M ² encoding is 2.5T (where
T is the length of the bit cell of the signal before coding, and is the reciprocal of the data rate. ) And a data pattern with a signal transition interval of 2.5T, and the signal transition interval is
Becomes more 3.5T, the data pattern is provided at least one that can serve as unique in the data stream of M ² code.

(C) At the end of the sync data pattern, a fixed data pattern for setting the end DSV of the sync data pattern to zero is provided.

[Action]

The present invention, a unique sync pattern provided at an arbitrary position of the M ² encoding before digital signal, and modulated by M ² code.

In the above-described "0" data, DSV is caused to complete the pattern of the three types defined in M ² code modulation rule. Note that the three patterns are as follows.

Then, the control bit, which is arranged next to the “0” data and whose polarity is controlled in accordance with the DSV at the end of the “0” data, sets the DSV at the bit cell end of the control bit to 0, and in that state the sync data The pattern starts.

Specifically, the DSV of the data block of the digital signal
, Although vary within a range of ± 1.5 by M ² coding, possible values of the DSV at the boundary of any bit cell ± 1, 0
Will be one of Therefore, at the beginning of the sync pattern, the DSV takes any value of ± 1, 0, and there are six possible forms of DSV change at that stage (ie,
For each of the three points, the DSV has two trends, a decreasing trend and an increasing trend).

However, due to the above-mentioned "0" data, the DSV line is inverted only to the zero point at the two points on the bit cell start side ± 1 of the "0" data. Therefore, there are four types of DSV changes in the bit cell of “0” data (DSV =
1 is decreasing direction, DSV = 0 is increasing and decreasing direction, DSV =-
The DSV at the bit cell end of “0” data is ± 1,0.

In the control bit cell, since "1" or "0" is inserted according to the DSV at the end of "0" data, the DSV at the end of the control bit becomes 0 (that is, DSV = ± 1). Is "0" for DSV = 0 and "1" for DSV = 0).

As a result, of the sync patterns [sync data patterns] having the same unique pattern, the minimum number of bits, that is, the shortest sync pattern [sync data pattern] is generated.

The sync data pattern following the control bit is
Since the M ² code modulation rule is a unique pattern that is not formed, to match the data in the data stream that is modulated by the M ² code is not obtained there unless an error occurs, Therefore, the sync pattern can be easily detected, and erroneous detection can be prevented.

In addition, since the DSV at the end of the sync data pattern is set to zero by the fixed data pattern following the sync data pattern, the data following the sync pattern starts from DSV = 0. As a result, the DSV of the data portion following the sync pattern can be set to within ± 1.5 and can be made DC-free.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIGS. 1 to 9, the present invention is applied to a sync pattern of an 8-bit cell [8T]. This description will be made in the following order.

(A) Regarding the configuration and operation of the frame synchronization system, (A-1) Encoder side (A-2) Decoder side (B) About unique sync pattern (sync data pattern), (B-1) Sync pattern configuration (B-1-1) About "0" data and control bits (B-1-2) About sync data pattern (B-2) About changes in sync pattern and DSV (A) Configuration and operation of frame synchronization system 1 to 6 show the configuration of a system for carrying out the present invention. The description will be made in the following order.

(A-1) Encoder Side FIGS. 1 to 3 show the configuration of the frame synchronization system on the encoder side.

The 8T sync pattern P _SY applied from the terminal 1 or the original digital data D _ori as a digital signal is M ²
The inversion control signal generation circuit 2 (hereinafter, referred to as a control signal generation circuit) and the inversion inhibition control circuit 3 are supplied. Disable inversion control circuit 3 and the control signal generation circuit 2 operates in synchronism with the clock signal S _CK of the frequency of the bit cell input from the terminal 4.

The control signal generating circuit 2, based on the M ² code modulation rule, the sync pattern P _SY is supplied, or to form an inverted control signal S _INC from the original digital data D _ori, and outputs to the AND gate 5.

In Disable inversion control circuit 3, while the sync period signal S _SYT indicating a sync insertion period is applied from the terminal 7, predetermined inversion prohibition sync pattern P _SY that are sequentially supplied by the clock signal S _CK When a location is detected, an "H" level inversion inhibition signal _SIOF is output to the AND gate 5. The output of the inversion inhibition signal _SIOF in other periods is at the “L” level.

In the AND gate 5, when the input inversion prohibition signal _SIOF is at the "L" level, it is inverted by the inverter to the "H" level, so that the inversion control signal S _INC output from the control signal generation circuit 2 is output. JK flip-flop 6
J-KFF]. And J,
RF data is output from the Q terminal every time the clock signal _S2CK falls from the terminal 8 according to the input state of both K terminals. Clock signal S _2CK is obtained by doubling the clock signal S _CK of the frequency of the bit cell.

Also, when the above-mentioned inversion inhibition signal _SIOF is at “H” level,
Since the input side of the AND gate 5 is inverted to the “L” level, the output of the AND gate 5 is set to the “L” level.
Applied to both J and K terminals. Therefore, the J-KFF 6 holds and outputs the previous RF data.

The circuit operation on the encoder side will be described with reference to FIGS.

While the original digital data D _ori is being applied to the terminal 1, the “L” level output from the inversion inhibition control circuit 3 is applied to the AND gate 5 as described above. This output is inverted to “H” level, so that the inverted control signal S _INC from the control signal generation circuit 2 is used as it is in the J-KFF6.
Is supplied to both J and K terminals. Then, in accordance with the input states of the J and K terminals, the RF data is sequentially output in synchronization with the fall of the clock signal _S2CK .

Then, at a the inserted sync insertion period of the sync pattern P _SY, the control signal generation circuit 2, the sync pattern P _SY1 represented by NRZ ( "00000101") and the sync pattern P _SY2 ( "01000101") Both are supplied. Control signal generating circuit 2 selects one of the sync pattern P _SY according to the state of the original digital data D _ori. In addition, a sync period signal S _SYT is added to the inversion inhibition control circuit 3. Here, as shown in FIG. 2 A, as the sync pattern P _SY, the sync pattern P _SY1 "00 shown in NRZ
000101 "When is selected, the control signal generation circuit 2, the inverted control signal S _INC is formed. The inversion control signal S _INC, as shown in FIG. 2 C, data is" 0, " rises 2 / 1T than the second half of the bit cell in synchronization with the clock signal S _CK, in the case of "1" is to rise 1 / 2T in the first half of the bit cell. here, T is coded before Is the length of the bit cell of the signal, and is the reciprocal of the data rate.

In the case of this sync pattern _PSY1 , as described below,
Only the portion between the fourth and fifth bit cells is the inversion prohibition portion.

Accordingly, there is no inversion prohibition point between the other bit cells, and the inversion control signal S _INC is supplied to J-KFF6 as it is, as shown in FIGS. 2C and 2E.

Furthermore, the bit cell with inversion forbidden location, i.e., when the fourth bit cell BC4 sync pattern P _SY1 is detected by inverting prohibition control circuit 3, as shown in FIG. 2 D, "H" level of the inverted prohibition The signal _SIOF is output from the inversion inhibition control circuit 3 to the AND gate 5. Therefore, an "L" level output from the AND gate 5 is applied to the J-KFF 6 as shown in FIG. 2E during the period of the bit cell BC4.

Hereinafter, the aforementioned sync pattern P _SY1 represented by NRZ is M
^{2 The} process of encoding will be described.

(A) In the first bit cell BC ₁ (“0”) of the sync pattern P _SY1 (“00000101”), since the condition for changing the Q output is not satisfied, if the initial Q output is zero,
The Q output of J-KFF6 becomes "00", as shown in FIG. 2G, and retains the previous state. In the 1 / 2T period later in this bit cell BC _1, the inverted control signal S _INC as Figure 2 C
Becomes "H" level, and is output directly to both J and K terminals of J-KFF6.

(B) In the second bit cell BC ₂ (“0”), FIG.
C, as shown in B, and at the beginning of the bit cell BC _2, J-
KFF6 of J, for K both terminals is "H" level, the fall of the clock signal S _2CK, Q output of the J-KFF6 become inverted and "11".

(C) Next, in the third bit cell BC ₃ (“0”), at the beginning, J-KF
The Q output of F6 is inverted to "00".

(D) In the fourth bit cell BC ₄ (“0”), FIG.
D, as shown in E, becomes a rise of the inverted inhibit signal S _IOF, the beginning of the bit cell BC _4, for J a J-KFF6, the K two terminals is still "H" level, the clock signal S _2CK With the fall, the Q output of J-KFF6 is inverted to "11".

(E) the J-KFF6 by fifth bit cell BC ₅ ( "0") in the inverted inhibit signal S _IOF became "H" level,
The “L” level is added, and as a result, the Q output becomes “11” while holding the output of (d).

(F) In the sixth bit cell BC ₆ (“1”), the inversion control signal S _INC becomes “H” only during the first half T period of the bit cell BC _6.
Level, which is added to J-KFF6. In this case, an input is "H" level of the J-KFF6, and position caused the fall of the clock signal S _2CK are the exactly middle of the bit cell BC _6, Q output of the J-KFF6, the bit cell BC Invert around the middle of ₆ . That is, in the first half of the bit cell BC _6, holds the previous output "1", in the second half and outputs the inverted to "0". Therefore, the Q output becomes "10".

(G) In the seventh bit cell BC ₇ (“0”), since the inversion control signal S _INC remains at “L” level as shown in FIG. 2C, the input of J-KFF6 also becomes “L” level. , Q outputs are kept at "00" while maintaining the state of (f).

(H) In the eighth bit cell BC ₈ (“1”), (f)
Q output is inverted at an intermediate bit cell BC ₈ in the same manner as. That is, in the first half of the bit cell BC _8, and outputs the holds the output "0" (g), in the second half inverted to "1". Therefore, the Q output becomes "01". Thus, "00" indicated by NRZ
The sync pattern P _SY1 of “000101” becomes “0011001111100001” in the process of (a) to (h), and the clock signal S
Sync pattern P _SY11 which is M ² code of 16 bits in accordance with the rate of _2CK is formed.

The output shown in FIG. 2H is also a pattern when the initial Q output of J-KFF6 is "1", and "0" and "1" are inverted with _respect to the above-mentioned sync pattern _PSY11. This is a sync pattern _PSY12 in the shape of a _circle . Also in the FIG. 3 shows a second diagram similar time chart when adopting shown in NRZ "01000101" as a sync pattern P _SY things, not described in detail. Thus, the aforementioned sync pattern P _SY11, P _SY12 same clock signal S M ² coding rate at the 16-bit _2CK been sync pattern P _SY21, P _SY22 is formed. The sync pattern P _{SY21 in} this case is (“ _{1110001111100001} ”), and the sync pattern P _SY22 is (“000111000001111”).
0 ").

(A-2) Decoder Side FIGS. 4 to 6 show the configuration of the decoder side of the frame synchronization system.

Each frame structure is supplied from a terminal 10 [sync pattern P _SY and the frame data consisting of a data block D _BL]
RF data with has a M ² decoder 11, the sync detecting circuit
12 and the PLL circuit 13.

PLL circuit 13 performs extraction of bit clock from the RF data and supplies the doubled clock signal S _2CK and M ² decoder 11 described above, the sync detection circuit 12.

M ² decoder 11, the RF data supplied from the terminal 10,
Based on the M ² code rules demodulates the original digital data D _ori, and outputs to the AND gate 14.

In the sync detection circuit 12, the RF data supplied from the terminal 10 is compared with a predetermined sync pattern _PSY . If the sync pattern _PSY is detected in the RF data, the control signal _Scon at the “H” level is supplied from the sync detection circuit 12 to the AND gate 14 and the output terminal 15. The control signal S _con input to the AND gate 14 is inverted to the “L” level, and as a result, the original digital data D _ori is not output from the AND gate 14. This state is maintained during the 8T sync period.

When the last bit of the sync pattern _PSY passes through the sync detection circuit 12, the control signal _Scon output from the sync detection circuit 12 becomes "L" level and is supplied to the AND gate 14 and the output terminal 15. Is done. At this time AND gate 14
Control signal S _con inputted to, since the inverted by "H" level, the original digital data D _ori demodulated by M ² decoder 11 is taken out is supplied to the output terminal 16.

Incidentally, M ² decoder 11 and the sync detection circuit 12, PLL circuit 1
It operates in synchronization with the clock signal _S2CK supplied from 3.

Thus, the in sync period (8T), the sync pattern P _SY is detected, in a period other than the sync period of the RF data, only the data block D _BL is decoded by the M ² decoder 11, the original digital data Restored to D _ori .

5 and 6 show examples of the sync detection circuit, respectively. The sync detection circuit 20 in FIG. 5 is a so-called shift register, and the shift register 20 is a 16-bit shift register that captures RF data in accordance with a clock signal _S2CK supplied from the PLL circuit 13 (the 16-bit shift register). Each signal of the bit is represented by a code A to P). When the RF data moves in the shift register 20 according to the clock signal _S2CK , the RF data is predetermined for each bit.
Matching with the 16-bit sync pattern _PSY is performed. If the sync pattern P _SY is detected in the RF data,
The sync detection circuit 20 outputs an “H” level control signal S _con
Is output.

Note that out of the 16 bits A to P, C and D are control bits. The probability that the sync pattern P _SY is detected by the sync detection circuit 20 is a 4/2 ¹⁶ = 1/2 ^14.

The sync detection circuit 25 shown in FIG. 6 is common among the 12 bits (E to P) of the four sync patterns P _SY11 , P _SY12 , P _SY21 , and P _SY22 except for the bits A to D. The two objects (P _SY11 and P _SY21 , P _SY12 and P _SY22 ) are grouped together and ANDed by the AND gates 26 and 27 first, and then O by the OR gate 28
By taking R, the sync pattern _{PSY is} to be detected. This probability of sync pattern P _SY is detected by is 2/12 ¹² = 1/2 ^11.

Or, four types of sync patterns P not shown
_{SY11 to PSY22} may all be connected by an OR gate. That is, when the detection probability of the logical expression Y = CDGHIJKP + ABCGHIJKP + ABEFLMNO + DEFLMNO this pattern becomes 4/2 ¹⁶ = 1/2 ^14.

(B) Unique sync pattern [sync data pattern] An example of a unique sync pattern [sync data pattern] will be described with reference to FIGS. 7 to 9.
FIG. 7 shows the overall structure of the sync pattern.
FIGS. A and D show _{DSVs of} sync patterns P _{SY11 to} P _SY22 .
(Digital Sum Variation) changes respectively shown in, FIG. 8 B and FIG C respectively show the waveform of the sync pattern P _SY11 and P _SY12. The figure shows a state transition diagram of the M ² code ninth.

(B-1) Configuration of Sync Pattern The sync pattern _PSY shown in FIG. 7 has an arbitrary data portion 30 and 1-bit “0” data 31 into which “0” is inserted.
And a 1-bit control bit 32 into which "0" or "1" is inserted, and a 5-bit sync data pattern 33. The length of the 8-bit cell (8T) excluding the data portion 30 is set. The sync data pattern 33 is composed of preceding and following fixed data patterns 34 and 35 (hereinafter, referred to as fixed patterns) and a unique data pattern 36 disposed between the fixed patterns 34 and 35. In this embodiment,
Description will be made assuming that an arbitrary data portion 30 is omitted.

(B-1-1) "0" for the data and control bits and "0" data 31, the control bits 32, the beginning of the sync pattern P _SY three ways based on the M ² code pattern And is used to set the DSV at the beginning of the sync pattern to zero. this is,
Sync pattern P with the same unique pattern
_This is for generating the shortest sync pattern P _SY [sync data pattern 33] among _SY [sync data pattern 33]. That is, the DSV of the M ² code, is between ± 1.5, also at the boundary of the bit cell, the value of DSV is 0, it is known that either of the ± 1.

Therefore, the end 37 of the data block _DBL shown in FIGS.
In this case, the DSV takes any value of ± 1, 0, and there are six types of DSV changes at that stage. The six reasons are that for each of the three points, the DSV has a decreasing tendency and an increasing tendency.

Therefore, following the data block D _BL, by placing a "0" data 31 described above, the bit cell of "0" data 31
Beginning of BC _1, i.e., to invert the lines in DSV to zero side both points of termination 37 side ± 1 of the data block D _BL. Therefore, "0" form of DSV changes in the bit cell BC ₁ data 31 becomes the four kinds only (DSV = 1 is decreasing direction (P _SY22), DSV = 0 is increased, a decrease in both directions (P _SY11, P _SY21 ), DS
V = -1 is the increasing direction (P _SY21) only), "0" DSV value at a bit cell BC ₁ the end 38 of the data becomes either ± 1, 0. As a result, the change in DSV is completed in one of the three patterns described above.

And in the bit cell BC _{2 of the} control bit,
Since data of “1” or “0” whose polarity is controlled to be inverted according to the DSV of the terminal 38 of the bit cell BC ₁ of “0” data is inserted, D at the terminal 39 of the bit cell BC ₂ of the control bit is inserted.
SV becomes 0 (that is, “0” for DSV = ± 1, DSV =
"1" for 0).

As a result, among the sync patterns _PSY having the same unique pattern, the shortest sync pattern _PSY can be generated, and the DSV of the entire sync pattern _PSY can be kept within a range of ± 1.5.

(B-1-2) Sync data pattern The sync data pattern 33 is provided following the control bit 32, and is a fixed pattern at both front and rear ends.
A unique data pattern 36 is arranged between 34 and 35.

However, a unique data pattern 36 in M ² code, from the M ² code modulation rule refers to a pattern having no signal transition interval be formed. For example,
As is apparent from the state transition diagram of FIG. 9, the M ² code,
2.5T followed by either 2T, 2.5T or 3T signal transition interval,
Or without their combination being continuous,
There is no pattern having a transition interval of 3T or more (for example, 3.5T). In short, after 2.5T, for example, 2T, 2.5T or 3
One or more T, or select multiple, if the data pattern 36 is continuously, to match the data modulated by M ² code is not obtained there unless the error occurs, This is a unique data pattern 36.

Therefore, a signal pattern having a continuous signal transition interval of 2.5T and 2T, such as the data pattern 36 of this embodiment, is a unique pattern.

As a result, the data pattern 36, to become a unique pattern that is not formed from the M ² code modulation rule, it is easy to detect the sync pattern P _SY, also prevent the sync pattern P _SY of false detection Is done.

“0” is inserted in the fixed pattern 34, and this fixed pattern 34 is for keeping the DSV of the sync data pattern 33 within ± 1.5. The fixed pattern 35, the DSV of the sync data patterns 33 is set to zero, the DSV of the data block D _BL followed is intended to fit within ± 1.5. That is, in the bit cell BC ₂ end 39 of the control bits 32, because it is the DSV = 0, "0" when there is no fixed pattern 34 that is inserted in the signal transition interval of the data pattern 36 is 2.5T In this case, DSV exceeds the range of ± 1.5. Also, DSV of data block D _BL
If DSV does not start from zero, the DSV of data block D _BL is ± 1.5
This is because the DC-free condition may not be satisfied in some cases.

It should be noted that a data pattern 36 of 3.5T or more may be used. At this time, the DSV of the sync data pattern 33 is ±
It can exceed 1.5.

By the way, as shown in FIGS. 8A and 8D, in order to secure a 2.5T signal transition interval,
The reversal prohibition point P _IOF has been set. This is (A-1)
As described in detail above, by applying an "L" level to both the J and K terminals of J-KFF6, the Q output is realized in a holding state.

As shown in FIGS. 8A and 8D, the bit _cells on both sides of the inversion prohibition point P _IOF , that is, the bit cells BC ₄ and BC ₅ are both “0”.
0 "is inserted. In a typical M ² code, inversion prohibited point
Tendency of the DSV is inverted by P _IOF, what was an increase or decrease in the bit cell BC ₄ is a decreasing or increasing tendency in the next bit cell BC _5. However, this inversion prohibition point P
Due to the setting of the _IOF , the DSV tends to be continuous in the bit cells BC ₄ and BC ₅ , and a signal transition interval over a period of 2.5 T or more is secured.

The following table summarizes the control bits 32 described above, the number of zeros in the digital signal, and the presence / absence of inversion inhibition.

The position of the inversion prohibition point changes depending on the set sync pattern _PSY .

(B-2) Change of sync pattern P _SY and DSV As described above, “0” data 31, control bit 32 (“0” or “1”), fixed pattern 34
( "0"), the data pattern 36 (2.5T + 2T), the data to be inserted into the fixed pattern 35 or the like, or collectively various constraints, when viewed in NRZ format, the following two patterns and the sync pattern P _SY Become.

That is, “00000101” (sink pattern P _SY1 ) “01000101” (sink pattern P _SY2 ) And, when these sync patterns P _SY1 and P _SY2 are represented by the clock rate of the clock signal S _2CK , (A-1)
The following four patterns are sync patterns as detailed in
_{PSY11 to PSY22} . That is, 0011001111100001 (sync pattern P _SY11 ) _{1110001111100001} (sync pattern P _SY21 ) 1100110000011110 (sync pattern P _SY12 ) 0001110000011110 (sync pattern P _SY22 ) ABCDEFGHIJKLMNOP These four sync patterns P _{SY11 to} P _SY22 are all 16
Bits are displayed and the sync pattern P _SY11 , P
_SY12 corresponds to the above-described sync pattern P _SY1, sync pattern P _SY21, P _SY22 corresponds to the above-described sync pattern P _SY2.

If the value of each bit is made to correspond to the change in DSV, the sync patterns P _SY11 , P _SY12 , P _SY21 , and P _{SY22 become respectively} FIG.
And FIG. 8D.

As is clear from FIGS. 8A and 8C, any of the patterns P _SY11 , P _SY12 , P _SY21 , and P _SY22 has DSV = 0 at the end 39 of the control bit 32 and has a fixed pattern. 34 by zero, prevents the sync data pattern 33 goes out of the range of ± 1.5 (DSV), and by providing the reversal prohibition point P _IOF in the data pattern within 36 2.5T data patterns 36 securing a transition interval, and a DSV end 40 of the sync pattern P _SY zero by more fixed pattern 35.

In this embodiment, the "0" data 31, the control bit 32, the fixed pattern 34, and the like are all 1 bit, but the present invention is not limited to this. Of course, it can be changed.

〔The invention's effect〕

According to the present invention, the data in the data stream that is modulated by the M ² code, mistake can be prevented from being detected as a sync pattern, thereby synchronization shift, it is possible to prevent the occurrence of synchronous error, the frame synchronization It is possible to obtain the digital signal accurately and stably and to reproduce the digital signal faithfully.

In addition, the shortest sync pattern among the sync patterns having the same unique pattern can be formed, but there is an effect that redundancy for frame synchronization is not increased.

Also, since the DSV at the end of the sync data pattern is set to zero by the fixed data pattern following the sync data pattern, the data following the sync pattern starts from DSV = 0, and thus the DSV of the digital signal following the sync pattern is Within the range of ± 1.5, DC free can be guaranteed, and the decoding circuit can be simplified by the above effects.

Furthermore, according to the embodiment, since the fixed data pattern is arranged before the data pattern, the entire sync data pattern can be kept within ± 1.5 of DSV, and the entire sync data pattern is in a DC-free state. There is an effect that can be maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram on the encoder side according to one embodiment of the present invention, FIGS. 2 and 3 are timing charts used for explaining the operation on the encoder side, respectively, and FIG. 4 is a decoder side according to one embodiment of the present invention. FIG. 5 is a circuit diagram showing an example of a sync detection circuit. FIG. 7 is a schematic diagram showing the configuration of a sync pattern. FIG.
Schematic diagram showing respective changes and V, Figure 9 is a state transition diagram for explaining the M ² code. Explanation of main symbols in the drawings 31: “0” data, 32: control bit, 33: sync data pattern, 34, 35: fixed data pattern, 36: data pattern, 37, 40: end, P _SY , P _SY11 , P _SY12 , P _SY21 , P
_SY22: sync pattern, T: length of the bit cell, BC _1, BC _2, B
_{C 3, BC 4, BC 5} , BC 6, BC 7, BC 8: bit cell.

Claims (2)

(57) [Claims] 1. A M ² at an arbitrary position of the coding digital signal before providing the sync pattern that satisfies the following requirements (a) to (c), the frame synchronization method comprising modulating the M ² code. (A) The sync pattern includes a sync data pattern consisting of a predetermined number of bits, “0” data provided prior to the sync data pattern, and between the “0” data and the sync data pattern. It consists of at least one control bit whose polarity is controlled to be inverted according to the DSV at the end of the "0" data so that the DSV at the beginning of the sync data pattern becomes zero. (B) The above sync data pattern, signal transition interval after receiving the M ² encoding is 2.5T (where, T
Is the length of the bit cell of the signal before encoding and is the reciprocal of the data rate. ) And a data pattern having a signal transition interval of 2.5T, which is provided following the data pattern of which the signal transition interval is 2.5T. , the data pattern that can serve as unique in M ² code of the data stream without pair in capital is provided at least one set. (C) At the end of the sync data pattern, a fixed data pattern for setting the end DSV of the sync data pattern to zero is provided. Wherein M ² in any position of the coded digital signal before providing the sync pattern that satisfies the following requirements (a) to (c), the frame synchronization method comprising modulating the M ² code. (A) The sync pattern includes a sync data pattern consisting of a predetermined number of bits, “0” data provided prior to the sync data pattern, and between the “0” data and the sync data pattern. At least one control bit whose polarity is controlled to be inverted according to the DSV at the end of the "0" data so that the DSV at the beginning of the sync data pattern is set to zero. (B) The above sync data pattern, signal transition interval after receiving the M ² encoding is 2.5T (where, T
Is the length of the bit cell of the signal before encoding and is the reciprocal of the data rate. ) And a data pattern consisting, be provided subsequent to the data pattern the signal transition interval is 2.5T, the signal transition interval by receiving coded becomes more 3.5T, in the data stream of the M ² code At least one type of data pattern that can be unique is provided. (C) At the end of the sync data pattern, a fixed data pattern for setting the end DSV of the sync data pattern to zero is provided.