JPH01151334A - Frame synchronizing method - Google Patents

Abstract

PURPOSE:To prevent a sync pattern from being detected erroneously by providing the sync pattern not being formed by the modulation rule of an M<2> code at an arbitrary position in a digital signal before M<2> coding being applied and performing modulation by the M<2> code after setting the DSV of the start and termination of the sync pattern at zero. CONSTITUTION:A unique sync pattern 36 is provided at the arbitrary position in the digital signal before the M<2> coding being applied, and is modulated by the M<2> code. In '0' data 31, the DSV is completed in three kinds of patterns regulated by the modulation rule of the M<2> code. And the DSV at the termination of a bit cell of a control bit 32 arranged at the next place of the '0' data 31 and whose polarity is inversely controlled corresponding to the DSV at the termination of the '0' data is set at '0'. A sync data pattern 33 following the control bit 32 is the unique pattern 36 not being formed by the modulation rule of the M<2> code, therefore, non coincidence with data in a data stream being modulated by the M<2> code is obtained. In such a way, it is possible to prevent the sync pattern from being detected erroneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization method, and particularly to a frame synchronization method for a digital signal modulated by an Mz code (M-square code).

[Summary of the invention]

In this invention, a unique sync pattern that cannot be formed from the Mt code modulation rule is provided at any position of the digital signal before M2 encoding, and the DSV at the beginning and end of this unique sync pattern is set to zero. After that,
The configuration is such that modulation is performed using an Mt code.

Therefore, the sink pattern can be detected easily and reliably.
Erroneous detection of sync patterns can be prevented, thereby preventing synchronization deviations and synchronization errors from occurring.

Frame synchronization can be achieved accurately and stably, and digital signals can be reproduced faithfully.

In addition, since the detection of the sync pattern becomes easy and reliable, the shortest sync pattern can be formed with the minimum number of bits, without increasing redundancy for frame synchronization. Furthermore, D of the digital signal following the sync pattern
SV can be kept within ±1.5, and a DC-free state can be guaranteed.

[Conventional technology]

Various modulation methods for digital signals have been proposed in the past, and one of them is the Mt code disclosed in Japanese Patent Laid-Open No. 114206/1983. The 20M2 code is a so-called DC-free code that is based on a mirror code and can remove the DC component of a modulated digital signal.

In the Mz code, if the length of the pit cell is T, the minimum reversal interval T'', s,, = wT, the detection window width T - = '
AT.

Maximum reversal interval T, Ax = 3 T, (T'sax
/ T-i-=3), which is a self-clocking code that is affordable as long as the data rate is not too high.

By the way, when reproducing digital signals, accurate frame synchronization must be achieved. For this purpose, it is necessary to provide a sync pattern in the digital signal that can be clearly distinguished from data. For example, in the 8-10 modulation method used in RDAT, it is possible to form a unique sync pattern (which does not occur in the data stream). However, in the Mt code described above, no unique sync pattern is defined in the coded digital signal.

Therefore, conventionally, before a data signal is Mt encoded, a pattern in the form of NRZ that does not appear in the data unless an error occurs and exists with a probability of being present is selected, inserted into the digital signal, and M8 It was code modulated.

[Problem that the invention seeks to solve]

As mentioned above, since a specific sync pattern is inserted into the digital signal, this sync pattern cannot be unique, and if a bit error occurs in a data block, the same pattern as the sync pattern cannot be used. There is a problem in that data blocks occur within a data block with a certain probability.

For this reason, the above-mentioned data may be mistakenly detected as a sync pattern, resulting in synchronization deviations and synchronization errors, making it difficult to achieve accurate frame synchronization, and making it difficult to accurately reproduce digital signals. There was a problem.

Further, in the conventional technology as described above, there is a problem that the data length of the sync pattern generally tends to be long and the redundancy for frame synchronization becomes high, and it has been desired to improve these problems.

Therefore, an object of the present invention is to provide a frame synchronization method that accurately and stably achieves frame synchronization, forms the shortest sync pattern, and further ensures that the digital signal following the sync pattern is DC-free. It is about providing.

[Means for solving problems]

In this invention, a sync pattern that satisfies the requirements (a) to (c) below is provided at an arbitrary position of a digital signal before M2 encoding, and the sync pattern is modulated by the M2 code.

(a) A sync pattern is a sync data pattern consisting of a predetermined number of bits, “0” data provided preceding the sync data pattern, “°O” data and the sync data pattern, and is located between the sync data pattern and the sync data pattern. and at least one control bit whose polarity is controlled to be inverted according to the DSV at the end of "0" data in order to make the DSV at the start end zero.

(2) The sync data pattern has a signal transition interval of 2°57 after M2 encoding (where T is the length of the pit cell of the signal before encoding,
It is the reciprocal of the data rate. ) and a data pattern with a signal transition interval of 2.5T, and when encoded, the signal transition interval becomes either 27° 2.5T or 3T. Either there is at least one data pattern that can be unique in the Mz code data stream, or the signal transition interval becomes 3°5T or more after being encoded, and At least one type of data pattern that can be unique is provided.

(c) A fixed data pattern is provided at the end of the sync data pattern to set the DSV at the end of the sync data pattern to zero.

[Effect]

In this invention, a unique sync pattern is provided at an arbitrary position of a digital signal before M2 encoding, and the digital signal is modulated with an M2 code.

In the aforementioned “0” data, the DSV is M! This can be completed into three patterns defined by the code modulation rules. Note that the three patterns refer to those shown below.

A pattern 1.11.111.1111.111・
・・IB pattern 00.010.01110.01
11...10 and placed next to the '0' data, '
The control bit whose polarity is inverted according to the DSV at the end of the 0'' data sets the DSV at the end of the bit cell of the control bit to O, and the sync data pattern begins in this state.

Specifically, DSV of a data block of a digital signal
Ha, M! Although it fluctuates within a range of ±1.5 due to coding, the possible value of DSV at any pit cell boundary is ±1.0.

Therefore, at the beginning of the sync pattern, the DSV is ±1.
It takes any value of 0, and there are six ways in which the DSV can change at that stage (that is, for each of the three points, the DSV has two ways, a decreasing trend and an increasing trend).

However, due to the above-mentioned “0” data, the DSV
The line is reversed only towards the zero point side. Therefore, there are four ways in which DSv changes in a pit cell with "0" data (DSV-1 is in the decreasing direction, DSV=O is in both increasing and decreasing directions, and DSV--1 is in the increasing direction. “0
``The DSV at the end of the data pit cell is ±1.0.

Therefore, in the control bit cell, "1" or 0' is inserted depending on the DSV at the end of the "0" data, so the DSV at the end of the control bit cell becomes 0 (that is, DSV=±1 “0” for DSV=O
“1”°).

As a result, among the sync patterns (sync data patterns) having the same unique pattern, the minimum number of bits, that is, the shortest sync pattern (sync data pattern) is generated.

The sink data pattern following the control bit is M
Since it is a unique pattern that cannot be formed from the modulation rules of the t-code, it is unlikely that it will match the data in the data stream modulated by the M2 code, except in the case of an error. Detection of the sync pattern becomes easier and false detection is prevented.

Further, since the fixed data pattern following the sync data pattern makes the DSv at the end of the sync data pattern zero, the data following the sync pattern starts from DSV=O. As a result, the DSV of the data portion following the sync pattern can be kept within ±1°5, making it DC-free.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIGS. 1 to 9,
This invention is applied to a sync pattern of an 8-bit cell [8T].

Note that this explanation will be made in the following order.

(A) Regarding the configuration and operation of the frame synchronization system, (A-1) Encoder side (8-2) Decoder side (B) Unique sync pattern [sync data pattern], (B-1) Configuration of sync pattern Regarding (It-1-
1) About "0" data and control bit (B-1-2) About sink data pattern (B-
2) Changes in sync pattern and DSV (A) Structure and operation of frame synchronization system FIGS. 1 to 6 show the structure of a system for implementing the present invention. They will be explained in order below.

(A-1) Encoder Side FIGS. 1 to 3 show the configuration of the encoder side of the frame synchronization system.

8T sink pattern PS Y added from terminal 1
+or original digital data D as a digital signal
ori is the inversion control signal generation circuit 2 for M2 (hereinafter referred to as control signal generation circuit) and the inversion prohibition near:/)t2-
are supplied to the small circuits 3, respectively. This control signal generation circuit 2
The inversion prohibition control circuit 3 operates in synchronization with a clock signal SCK of the bit cell frequency inputted from a terminal 4.

The control signal generating circuit 2 receives the supplied sync pattern P, 7° or the original digital data D based on the modulation rule of the y1t code. ,! An inverted control signal 5INC is formed and output to the AND gate 5.

The inversion prohibition control circuit 3 receives a sync period signal S indicating that it is a sync insertion period, 7. is applied from the terminal 7, when a predetermined inversion prohibited portion of the sync pattern psy that is sequentially supplied by the clock signal SCK is detected, an “H” level inversion prohibition signal S1° is output to the AND gate 5. do. The output of the inversion inhibit signal 5IOF during other periods is at the 'L' level.

In the AND gate 5, the input inversion inhibit signal S IO
When F is “L” level, it is inverted by the inverter and “
Therefore, the inverted control signal 5INC output from the control signal generating circuit 2 is applied to both terminals of the flip-flop 6 (hereinafter referred to as J-KFF). And J.

Depending on the input states of both K terminals, RF data is output from the Q terminal every time the clock signal S tcK from the terminal 8 falls. Clock signal S! □ is obtained by doubling the clock signal SC+C of the frequency of the bit cell.

Furthermore, when the above-mentioned inversion inhibit signal 5IOF is at the "H" level, it is inverted at the input side of the AND gate 5 and becomes the "L" level, so the output of the AND gate 5 is set to the "L" level, which causes J, is applied to both terminals. For this reason, J
-KFF6 holds and outputs previous RF data.

The circuit operation on the encoder side will be explained with reference to FIGS. 1 to 3.

Original digital data D. . Therefore, the inverted control signal 5INC from the control signal generation circuit 2 is supplied as it is to both the J and K terminals of the J-KFF6.Then, depending on the input states of both the J and K terminals, the falling edge of the clock signal S tCK RF data is sequentially output in synchronization with.

Next, in the sync insertion period during which the sync pattern psv is inserted, the control signal generation circuit 2 receives the sync pattern Psy+ (“00000101
) and sink pattern PRY□(“0100010
1"). The control signal generation circuit 2 selects one of the sync patterns psy according to the state of the original digital data D.ri. The inversion prohibition control circuit 3 is also supplied with a sync period signal psy. S svr is added.Here, as shown in FIG. 2A, the sink pattern p
sv, the sink pattern p svl" denoted by NRZ
00000101'' is selected, the control signal generation circuit 2 generates an inverted control signal 5INC.

This inverted control signal 5INc is, as shown in FIG. 2C,
When the data is "0", %T rises from the latter half of the bit cell in synchronization with the clock signal SCK, and '+1
In the case of 11, 'AT rises in the first half of the bit cell. Here, T is the bit cell length of the signal before encoding and is the reciprocal of the data rate.

This sink pattern P! In the case of Yl, as will be described later, only the portion between the fourth and fifth bit cells is prohibited from being inverted.

Therefore, there is no inversion prohibited portion between the other bit cells, and the inversion control signal S4° is directly supplied to the J-KFF6 as shown in FIGS. 2C and 2E.

Further, when the bit cell with an inversion prohibited portion, that is, the fourth bit cell BC4 of the sync pattern P svl is detected by the inversion prohibition control circuit 3, an "H" level inversion prohibition signal S1 is detected, as shown in the second diagram. °r is output from the inversion inhibition control circuit 3 to the AND gate 5. Therefore, during the period of bit cell BC4, AND gate 5
As shown in Figure 2E, the output of "L' lebel from J
- added to KFF6.

Hereinafter, the above-mentioned sink pattern P! expressed as NRZ will be described.
The process of M2 encoding of i will be explained.

(B) Sink pattern P3□ (“00000101”)
In the first bit cell BC, (“0”), the conditions for changing the Q output are not met, so assuming that the initial Q output is zero, the Q output of J-KFF6 is shown in Figure 2 G. becomes "00" and maintains the previous state. In addition, in the second half 'AT period of this bit cell BC, the inverted control signal 5INe becomes the 'Hn level as shown in FIG. 2C, and the J
-KFF617)J, is output as is to both terminals.

(b) In the second bit cell BCZ (“0°”),
As shown in FIGS. 2C and 2E, at the beginning of bit cell BC, both terminals of J-KFF6 are at 'H' level, so as clock signal SZCK falls,
The Q output of J-KFF6 is inverted and becomes "11".

(c) Next, in the third bit cell B C3 ("0"), the Q output of J-KFF6 is inverted to "00n" at the starting end in the same manner as in (b) above.

(d) In the fourth bit cell BC, (“0゛°),
As shown in the second diagram, E, the inversion inhibit signal S1°F rises, but at the beginning of the bit cell BC, J-K
Both J and K terminals of FF6 are still at “H” level, so
As the clock signal szct falls, J-KFF
The Q output of 6 is inverted and becomes "11".

(e) In the fifth bit cell B Cs (“O”),
J-
“L” level will be added to KFF6,
As a result, the Q output holds the output (d) and becomes “11”.
becomes.

(to) In the 6th bit cell BC, (1”), the inverted control signal 5INI: is +AT in the first half of the bit cell BC&
It is at "H" level only during the period, and this is added to J-KFF6. In this case, since the input of J-KFF6 is at "H" level and the position where the clock signal S2□ falls is exactly in the middle of bit cell B Ch,
The Q output number of J-KFF6 is inverted at the middle of this bit cell BC6. That is, the first half of the bit cell BC holds the previous output "+In", and the second half inverts and outputs "0". Therefore, the Q output becomes "10".

(g) 7th bit cell BC? (“0”), the inverted control signal 5INe remains at the “L” level as shown in Figure 2C, so the input of the J-KFF6 also becomes the “L” level, and the Q output maintains the (to) state. and is set to "00".

(h) In the 8th bit cell BC, (“1”), (
), the Q output is inverted in the middle of the bit cells BC. That is, in the first half of the bit cell BCs, (T)
The NRZ
“oooo.”

The sync pattern P, □ of 101" becomes "0011001111100001" through the steps (a) to (h), and a 16-bit M2-encoded sync pattern P5VII is formed according to the rate of the clock signal Szcw. .

Note that the d output shown in Figure 2F is the initial Q of J-KFF6.
This is also the pattern when the output is ``'1pa'', and is a sync pattern P!Yl! in which ``0'' and ``1pa'' are inverted compared to the sync pattern Pill described above.
Although not described in detail, the figure shows N as a sink pattern PSV.
A time chart similar to that shown in FIG. 2 is shown when "01000101" indicated by RZ is adopted. As a result, the above-mentioned sink patterns P, y, l.

P, 1 at the rate of clock signal S tcK as in □2
6-bit Mt encoded sync pattern P, 7□
,P. 2 is formed. Sink pattern P in this case
SVt is ("1110001111100001"
), and the sink pattern P S'fZt is (”
0001110000011110").

(A-2) Decoder side FIGS. 4 to 6 show the configuration of the decoder side of the frame synchronization system.

RF data having each frame structure [frame data consisting of a sync pattern psv and a data block DIIL] supplied from the terminal 10 is sent to the Mz decoder 11,
The signal is supplied to the sink detection circuit 12 and the PLL circuit 13, respectively.

The PLL circuit 13 extracts a pit clock from the RF data, and converts the doubled clock signal S2□ into the above-mentioned M
! The signal is supplied to the decoder 11 and the sync detection circuit 12.

The M2 decoder 11 converts the RF data supplied from the terminal 10 into M! Based on the code rules, it is demodulated into original digital data Dori and output to the AND gate 14.

In the sink detection circuit 12, the RF signal supplied from the terminal 10
The data is compared with a predetermined sync pattern psv. If the sync pattern psv is detected in the RF data, the sync detection circuit 12 outputs “
H” level control signal 5C (Ill is AND gate 14
and is supplied to the output terminal 15. The control signal Scon inputted to the AND gate 14 is inverted and becomes the "L" level, and as a result, the original digital data Deri is not output from the AND gate 14. This state continues for the 8T sync period.

Then, when the final bit of the sync pattern psv passes through the sync detection circuit 2, the sync detection circuit 12
The control signal S coo output from the control signal S coo becomes “L” level and is supplied to the L AND gate 14 and the output terminal 15 . At this time, the control signal S c input to the AND gate 14
Since oa is inverted and becomes the "HII level," the original digital data D or demodulated by the M2 decoder 11 is
i is supplied to the output terminal 16 and taken out.

Note that the M2 decoder 11 and the sync detection circuit 12 are connected to the PL
It operates in synchronization with the clock signal SICK supplied from the L circuit 13.

In this way, during the sync period (8T), the sync pattern psy is detected, and during the period other than the sync period, the RF
Among the data, only data block DIIL is M! Decoded by the decoder 11, the original digital data D,1!
will be restored.

FIGS. 5 and 6 show examples of sync detection circuits, respectively. The sync detection circuit 20 in FIG. 5 is a so-called shift register, and this shift register 20 is a PLL circuit 1.
According to the clock signal S tCK supplied from R
It is a 16-bit signal that takes in F data (note that each of these 16-bit signals is represented by the symbols AP). R
The F data is passed through the shift register 20 by the clock signal s.
While moving according to tcx, this RF data is checked against a predetermined 16-bit sync pattern PAY for each bit. If the sync pattern P3V is detected in the RF data, the sync detection circuit 20 outputs an "H" level control signal S con.

Note that among the 16 bits up to AND, C and D are control bits. The probability that the sync pattern PS"f is detected by the sync detection circuit 20 is 4/2'6=1/
It is 2I4.

The sync detection circuit 25 in FIG. 6 uses the aforementioned four sync patterns Psv■+P5vIt+P5v
Remove each bit of A-D from tr+P 5v2t<
Among the 12 bits (E to P), select two common bits (P svth and P SY!li P sy+t and P
5vzt) First, use AND gate 26.27 to A.
The sync pattern psv is attempted to be detected by taking the ND and then performing the OR at the OR gate 28. The probability that the sync pattern psv is thereby detected is 2/2''=1/2''.

Alternatively, four types of sink patterns psv (not shown)
□〜P! 'ftt may all be combined by an OR gate. That is, logical formula Y=λ100CDRvGHIJKUMNOP+AB
C115UP'GHI JKUIIQP+ABcr5E
FdHT': JKL, MNOP+λ100 CDEFGHT Ding KLMNOI' For this pattern, the detection probability is 4/2+
It becomes 6-1/2+4.

(B) Unique sync pattern (sync data pattern) An example of a unique sync pattern (sync data pattern) will be explained using FIGS. 7 to 9. FIG. 7 shows the overall configuration of the sync pattern, and FIG. 8A and the same figure show the sync pattern PS'1. ""PS'
ftt's DSV (Digital Sum Va)
FIGS. 8B and 8C show the waveforms of the sync patterns P, □1 and PSfIt, respectively. FIG. 9 shows a state transition diagram of the M2 code.

(B-1) Regarding the structure of the sync pattern The sync pattern psv shown in FIG.
The length of the cell is 8 bits (8T) excluding a 1-bit control bit 32 into which 1, 0, or 1n is inserted, a 5-bit sync data pattern 33, and a data portion 30. The sync data pattern 33 also includes fixed data patterns 34, 35 (hereinafter referred to as fixed patterns) before and after the fixed data pattern 34.35.
It consists of a unique data pattern 36 arranged between 35 and 35. Note that this embodiment will be described on the assumption that an arbitrary data portion 30 is omitted.

(B-1-1) About “0” data and control bits “0” data 31 and control bits 32 have three patterns A pattern based on the “M” code at the start end of the sync pattern PAY 1.11. 111.1111.111・
・・IB pattern 00.010.01110.01
11...102'', and is used to zero the DSV at the starting end of the sync pattern.This is used to complete the sync pattern Ps with the same unique pattern
This is to generate the shortest sync pattern PsvC sync data pattern 33] among y (sync data patterns 33). That is, the DSV of the y1t code is ±1.
5, and at the boundary of the bit cell, the DSV value is 0. It is known that it is either ±1.

Therefore, at the terminal end 37 of the data block DIL shown in FIGS. 8A and 8D, DSV takes a value of ±1 or 0,
There are six possible forms of change in DSV at that stage. These six reasons are for each of the three points.
This is because DSV has two trends: a decreasing trend and an increasing trend.

Therefore, following the data block DIIL, the above-mentioned “O
``By arranging data 31, the starting end of the bit cell BC of 3 pieces of ``0'' data, that is, the data block DIIL.
The DSV line at the pixel on the terminal end 37 side ±1 is inverted to the zero point side. Therefore, there are four forms of change in DSV in °゛0''0'' data 31 to cell BC, (
DS, V=1 only in the decreasing direction (P 5vzz), DSV
=O increases.

Decrease in both directions (P3YII, Psvz+), DS
V=1 is in the increasing direction (P, 7□, ) only), and the value of DSV at the terminal end 38 of the bit cell BC of "0" data is either ±1 or 0. As a result, the change in DSV is completed in one of the three patterns described above.

And in the control bit bit cell BC2,
DSV at the terminal 38 of the data bit cell BC
1”° or “°0°” whose polarity is inverted depending on the
data is inserted, the DSV at the terminal end 39 of the control bit bit cell BC becomes 0 (i.e., D
For SV=±1, b As a result, the shortest sink pattern psy can be generated among the sink patterns psy having the same unique pattern, and the DSV of the entire sink pattern psv can be ±
It can also be kept within the range of 1.5.

(B-1-2) About the sync data pattern The sync data pattern 33 is provided following the control bit 32, and has fixed patterns 34.
The configuration is such that a unique data pattern 36 is arranged between the data patterns 35 and 35.

By the way, the unique data pattern 36 in the M2 code refers to a pattern having a signal transition interval that cannot be formed according to the modulation rules of the M2 code. For example, as is clear from the state transition diagram in FIG. 9, in the Mt code, any one of the signal transition intervals of 2T, 2.5T, or 3T after 2.5T, or a combination thereof, occurs without consecutive , there is no pattern with a transition interval of 3 T or more (for example, 3.5 T). In short, 2.5
Next to T, for example, select 2T, 2.5T, or 3 or more, or select more than one, and consecutively create data pattern 3.
6, it is impossible for the data to match the data modulated with the M2 code except when an error occurs.
This is a unique data pattern 36.

Therefore, the data pattern 36 of this embodiment, in which the signal transition intervals are successive at 2.5T and 2T, is a unique pattern.

As a result, the data pattern 36 becomes a unique pattern that cannot be formed from the modulation rules of the M2 code, making it easy to detect the sync pattern psv and preventing erroneous detection of the sync pattern PSV.

The fixed pattern 34 has “0°” inserted, and this fixed pattern 34 is the DS of the sync data pattern 33.
This is to keep V within ±1.5. Further, the fixed pattern 35 sets the DSV of the sync data pattern 33 to zero, and sets the DSV of the following data block D□ to ±1.5.
This is to keep it within the range. That is, at the terminal end 39 of the bit cell BC of the control bit 32, DSV=
Therefore, without the fixed pattern 34 in which "0" is inserted, if the signal transition interval in the data pattern 36 is 2.5T, the DSV will exceed the range of ±1°5. This is because it will be put away. In addition, data block DIIL
DSV of data block D1 must be started from zero.
This is because SV may not fall within ±1.5, and the DC-free condition may not be satisfied.

Incidentally, as the data pattern 36, a pattern having a length of 3.5 or more may be used. D of sink data pattern 33 at this time
SV may exceed ±1.5.

Incidentally, in order to ensure a signal transition interval of 2°5T, an inversion prohibition point P1° is set in this data pattern 36, as shown in FIGS. 8A and 8C. this is,(
As described in detail in A-1), by applying the "1.

As shown in FIGS. 8A and 8D, "'oo" is inserted into the bit cells on both sides of the inversion inhibited point PIG, that is, the bit cells BC4°BC. In the normal M2 code, the tendency of DSV is reversed at the inversion prohibition point PI (IF), and the tendency of increasing or decreasing in bit cell BCa is the next bit cell BC.

There is a tendency to decrease or increase. However, due to the setting of this inversion prohibition point PIOF, bit cells BC, , BC
At s, the DSV trend becomes continuous, ensuring a signal transition interval of 2.5T or even longer.

The table below summarizes the aforementioned control bit 32, the number of zeros in the digital signal, and whether or not inversion is prohibited.

Note that the position of this inversion prohibition point changes depending on the set sync pattern PS''l.

(B-2) Changes in sync pattern P3'f and DSV As described above, "0"' data 31. Control bit 32 (“O++ or “1llll”), fixed pattern 34 (“0”), data pattern 36 (2,5T+
2T), data to be inserted into the fixed pattern 35, etc.
Alternatively, when various constraint conditions are put together and displayed in NRZ format, the following two patterns become the sink pattern Pal/.

That is, “00000101” (sink pattern P sv
+”) “01000101” (sync pattern psy□
) Then, if these sync patterns P3□, P, and 7□ are expressed by the clock rate of the clock signal 5zcx,
As detailed in (A-1), the following four patterns are sink patterns PSY□ to psv. becomes. That is, 0011
001111100001 (sink pattern P, vI
I) 1110001111100001 (Sink pattern P svz+) 1100110000011110
(Sink pattern Psy+z)0001110000
011110 (Sync pattern p svzz) ABC
DEFGHIJKLMNOP These four sink patterns P, □, ~psy□2 are
All are displayed in 16 bits, and the sync pattern P, □
In Psy+□ corresponds to the above-mentioned sink patterns P and □, and the sink pattern PSY! I+PSY2
□ corresponds to the above-mentioned sync pattern p svz.

When the value of each bit corresponds to the change in DSV, the sink pattern P 3Y11+ P 5vIt+ P s
vz++ P 5vzz are shown in Figures 8A and 8, respectively.
As shown in the figure.

As is clear from FIGS. 8A and 8C, which patterns P, □3. P, □2+ PM'f□* ps
vzt is also DS at the end 39 of the control bit 32.
■ = 0, and by setting the fixed pattern 34 to zero, the sink data pattern 33 is ±1°5 (DS
V), and by providing an inversion prohibition point PIOF within the data pattern 36, a transition interval of 2.5T of the data pattern 36 is ensured, and furthermore, the fixed pattern 35 is used to secure the transition interval of 2.5T of the sync pattern PSY. 40
The DSV of is set to zero.

In this embodiment, "0°" data 31. Control bit 32. Although the fixed patterns 34 and the like are all 1 bit, they are not limited to this, and of course can be changed to correspond to a sync pattern of any length.

〔Effect of the invention〕

According to this invention, it is possible to prevent data in a data stream modulated by an M2 code from being mistakenly detected as a sync pattern, thereby preventing the occurrence of synchronization deviations and synchronization errors, and ensuring accurate frame synchronization. Moreover, it has the effect that it can be stably obtained, and that the digital signal can be reproduced faithfully.

Another advantage is that the shortest sync pattern can be formed among sync patterns having the same unique pattern without increasing redundancy for frame synchronization.

Furthermore, the fixed data pattern following the sync data pattern makes the DSv at the end of the sync data pattern zero, so the data following the sync pattern starts from DSV=O, and as a result, the digital signal following the sync pattern starts from DSV=O. DSv can be kept within ±1.5, DC free can be guaranteed, and the decoding circuit can be easily constructed due to the above-mentioned effects.

Furthermore, according to the embodiment, since a fixed data pattern is placed before the data pattern, the entire sync data pattern can be kept within ±1.5 of DSV, making the entire sync data pattern DC-free. This has the effect of maintaining the state of

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the encoder side of an embodiment of the present invention, FIGS. 2 and 3 are timing charts used to explain the operation of the encoder side, and FIG. 4 is a block diagram of the decoder side of an embodiment of the present invention. The block diagram, FIGS. 5 and 6 are circuit diagrams showing examples of the sync detection circuit, FIG. 7 is a route diagram showing the configuration of the sync pattern, and FIG. 8 is the D of the sync pattern.
A route map showing changes in SV, and FIG. 9 is a state transition diagram for explaining the Mt code. Explanation of main symbols in the drawings 31: “'0” data, 32: Control bit, 33: Sink data pattern, 34, 35:
Fixed data pattern, 36: Data pattern, 37
, 40: Termination, P sv* P 5vrr+ P
sv1□, P, 7□, Psvz□: Zinc pattern, T2-bit cell length, B Cr, B
Cz, B C! , B Ca, BCs, B C
b, B C? , B C1l: Bit cell. Agent Patent Attorney Tadashi Sugiura Tomo 2 Imink + - 1 Timing Figure A & J Figure 1 Cd Figure 11 Figure 8

Claims (1)

[Claims] A frame characterized in that a sync pattern satisfying the requirements (a) to (c) below is provided at an arbitrary position of a digital signal before M^2 encoding, and the frame is modulated with an M^2 code. Synchronization method. (a) The sync pattern includes a sync data pattern consisting of a predetermined number of bits, "0" data provided preceding the sync data pattern, and between the "0" data and the sync data pattern, In order to set the DSV at the beginning of the sync data pattern to zero, set it to “0” above.
and at least one control bit whose polarity is controlled to be inverted according to the DSV at the data end. (2) The above sync data pattern has a signal transition interval of 2.5T (after undergoing M^2 encoding).
However, T is the length of the bit cell of the signal before encoding, and is the reciprocal of the data rate. ) and the data pattern with a signal transition interval of 2.5T are provided consecutively, and by being encoded, the signal transition interval becomes one of 2T, 2.5T, and 3T. There is at least one set of data patterns that can be unique in the M^2 code data stream, or the signal transition interval becomes 3.5T or more due to encoding, and the above M^ At least one type of data pattern is provided that can be unique in the two-code data stream. (c) A fixed data pattern is provided at the end of the sync data pattern to set the DSV at the end of the sync data pattern to zero.