JPH0256118A - Code converter - Google Patents

Abstract

PURPOSE:To convert an 8-bit data word into a 12-bit code word directly by making a code word group including at least one code word or over to each data word, and selecting a code word W2 from the code word group. CONSTITUTION:A selection signal generating circuit 8 generates a selection signal S, the selection signal S changes over a switch 9 to select either a code word from a code word generating circuit 2 or a code word from a code word generating circuit 3. A parallel/serial converter 10 converts the code word in 12-bit parallel appearing at an output of the switch 9 into a serial code. Then switches 16-18 selects and outputs each signal from a synchronizing pattern generating circuit 14 while a synchronizing pattern period signal from a counter 15 is set.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a 7L/7 device used for recording digital signals.
Run Length Llmlte
d) It relates to a code conversion device for realizing a code.

Conventional technology When recording digital data at high density on magnetic tape or disk, run-length limited codes (
(hereinafter referred to as RLL code) is used.

RLL code converts an m-bit data word into an n-bit code word, and then connects the converted n-bit code words. Say the sign that is restricted to .

Assuming that the 1-bit length of a data word is T, the following three conditions are known as desirable conditions for an RLL code suitable for high-density recording.

(1) The detection window width Tv (:m/1・T) is large (
2) The R small inversion interval TffIIn (=d-Tw) is large. (3) The maximum number of consecutive bits k is small. The larger the detection window width TV, the more jitter and peak shift in the reproduction process etc. The smaller the influence of time axis fluctuations on the decoding error rate and the larger the minimum inversion interval Tnln, the smaller the maximum number of consecutive bits k due to the influence of the high frequency component cutoff characteristics of the recording/reproducing system. The easier it is to obtain a self-clock function that extracts clock information from the reproduced signal.

In addition to the above three points, in the case of digital video signals that are normally expressed in 8 bits, it is desirable to be able to convert data words into code words in 8-bit units in order to avoid error propagation during the decoding process. There is.

Conventionally, various RLL codes have been developed from the above point of view, including 2/3 conversion codes (Franaszek et al.
, USP 3°889.899) is one of them. 2
According to the above definition, the /3 conversion code has d=2. ni=9. T
W = 0.667T, and when converting a 2-bit data word to a 3-bit code word, and when converting a 4-bit data word to a 6-bit code word.
Variable length R to switch the case of converting to a bit code word
It is an LL code.

Problems to be Solved by the Invention The above-mentioned 2/3 conversion code is an excellent RLL code that satisfies the conditions (1) to (3) above. ing. For this reason, for example, when converting the code of digital image data expressed in 8 bits, the delimiter between data words is 8 bits per word of image data.
It may span words.

In such a case, an error in one code word during decoding is propagated (expanded) to two words in the 8-bit image data.

Although RLL codes are used for the purpose of not deteriorating the decoding error rate even when performing high-density recording,
Since the /3 conversion code is a variable length code, decoding errors will be increased. In particular, digital V for home use
Because of the need for long-term recording in TR and other devices, the recording density is increased to near the limit. Therefore, the number of code word errors during the reproduction process increases significantly, and error propagation (expansion) also occurs frequently. This is a serious problem that must be resolved.

On the other hand, normal digital recording uses a format in which multiple pieces of data are treated as one block and a synchronization pattern is added to each block for block synchronization, and this synchronization pattern never appears in normal data. Selecting a special pattern. However, it is difficult to find such a synchronization pattern with the 2/3 conversion code.
Another problem with synchronization patterns is that they usually ignore restrictions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a code conversion device that solves the problems of the conventional example.

Means for Solving the Problems The present invention converts an m-bit data word into an n-bit code word, and connects the converted code words so that the number of consecutive bits of the same binary value in a bit string is 6 or more. A code converting device for generating a run-length limited code limited to the following: a code converting means in which each data word is associated with a code word group including at least one code word; A code word selection means selects a code word W2 from the code word group generated by the code conversion means, and a code word Wl immediately preceding the code word W2 is selected from the code word group to which it belongs based on the selection result of the code word W2. codeword modification means for modifying the selection; provisional decoding means for generating identification codes for each of a plurality of bit patterns obtained by dividing the codeword; sign inversion means for generating related values;
and data word decoding means for generating a data word corresponding to the code word by modifying the output of the code inverse conversion means according to the characteristics of the code word.

Operation The present invention provides the preceding code word W1 and the code word W following Wl.
2, or both. As a result, the number of code words constituting an RLL code is increased compared to before, and 8-bit data words, which were previously impossible, can be directly converted to 12-bit code words, and d=2. An RLL code that satisfies the restriction that = io is obtained (Tv:
0.6877), eliminating error expansion.

Furthermore, when decoding a data word from a code word, the data word is decoded based on the identification code for each of a plurality of bit patterns obtained by dividing the code word, instead of directly referring to the code word. Therefore, the number of bits referred to during decoding can be made smaller than the number of pits in the code word. As a result, the number of circuit elements required for decoding can be significantly reduced.

Example Next, the present invention will be explained in detail using examples.

For convenience of explanation, parameters representing characteristics of code words as shown in FIG. 2 are determined in order to classify code words used in the present invention. That is, L block: Starting end of a code word where I-bit identical binary value TB continues R block: End end portion of a code word where r-bit identical binary value LB continues: b (=12-1-r) Intermediate part of bit code word Code words used in the present invention are limited to those that satisfy the following conditions.

(+) 1≦1≦9, 1≦r≦9 (+) In the B block, the d and k limits are completely satisfied. (except when b=0). Furthermore, with respect to l and r, the following parameters F,
Introduce E.

The four parameters thus determined (TB, F, E, LB
), the connection between codewords is controlled based on the R block of codeword WI and the connection between the first codeword w1 and the second codeword W2 shown in FIG. Also at the connection part by the L block of code word W2, d,
This means trying to satisfy the k limit. Hereinafter, the rules regarding the connection between code words will be referred to as a connecting agent.

Table 1 shows the four parameters (Tllll, F, E,
Table 1 shows the rules for matching codeword sets according to the present invention, which are defined based on LH). In Table 1, CW-No is the combination number of code words and the identification number of the code words that make up the combination, and the code words that make up one combination are made to correspond to data words with the same =.

TB, F , E , and LB in Table 1 are parameters related to code words, and the example shows an example of a code word that can be represented by the parameters. Next, the code word combination rules in Table 1 will be explained in detail. In addition, the code word in which all 1's in code word A are replaced with 1's is replaced with code word A.
It is called the back pattern of , and is expressed as "A".

(1) F≠1. The code word C41 (F, E, 1) with E≠1, TB=1, and LB=1 is its back pattern CI!
(F, E, 1)' and CWf (F, E, 1) and F, E,
The values of TB are equal and the code word CW (F, E, 0
) and its back pattern CW (F, E, 0)'.

(CW-No, = 1.4.13) (2) Code word CW of F≠1, E=1, TB=1
(F, 1.X) il, its back pattern GW (F, 1
,X)'.

Note that X represents both O and 1.

(GW-No, = 2.3, 14.15) (3) F = 1.
The code word cw(1
,E,1) is CV(1,E,1) and F,E,Ti1l
are the same and are combined with the code word CW (1, E, 0) where LB=O.

(CW-No, = 5.G, 11.12) (4) F = 1
, E=1 code word cw (t, t, X) and its back pattern CW (1, 1,

((J-No, = 7.8, 9.20) With the combinations of code words (1) to (4) shown above, as shown in Table 2, even when code words are connected, d, k restrictions can be satisfied.

Among the 12-bit codewords, only the codewords that satisfy the above conditions (+) and (+) are combined according to (1) to (4), and the number of codeword pairs obtained is as follows: As shown in Table 3, it is 264. In addition, DP in Table 3
is the difference between the number of 1 and O in the codeword Table 3.1 (blank below) Table 3゜Table 3゜Table 3゜Table 3゜Table 3.7' (blank below) (Disparity ) represents the absolute value of

Since the number of 8-bit data words is 256, d=2. A 12-bit RLL code that satisfies =10 can convert all 8-bit data words.

By the way, in normal digital recording, multiple pieces of data are
A format in which a synchronization pattern for block synchronization is added to each block is used. As this synchronization pattern, a special pattern that never appears in normal data is selected.

In the present invention, code words that correspond to data words are limited to code words with a DP of 6 or less in Tables 3.1 to 3.6 (256 words), and the same code words with a DP of 8 are used as synchronization patterns. A pattern in which two words (F=1.E=1) are arranged in series is used (for example, code word 25B in Table 3.7).

As shown in FIG. 4, in any consecutive 12 bits (B12) of this 24-bit synchronization pattern, there is always a bit (b+:I=1-B) that constitutes a code word with a DP of 8. Since it is included, the DP of B12 is also 8.

On the other hand, the 24 bits include at least one 12-bit code word. Therefore, D corresponding to the data word
Any 24 bits of a bit string generated by connecting code words in which P is 6 or less always includes a portion where DP of 12 bits therein is 6 or less. For these reasons, this synchronization pattern never appears in a bit string obtained by connecting code words corresponding to data words.

As Kaneko explained, by determining the code word that corresponds to the data word and the code word used for the synchronization pattern, d = 2.
Correct block synchronization can be guaranteed while keeping k = 10.

Next, means for realizing the present invention will be explained using FIG. 1. In FIG. 1, a holding circuit 1 sequentially holds 8-bit data words sent periodically. Holding circuit 1
The outputs are input to the codeword generation circuit 2 and the codeword generation circuit 3.

In the codeword generation circuit 2, the "'codeword" of E=1 and the "°codeword 1'' of E≠1 in Table 3, their codewords, the parameter F regarding the R block,
Generate E. Here, the code word appearing at the output of the code word generation circuit 2 is assumed to be CW+.

On the other hand, the code word generation circuit 3 generates "code word 2" in Table 3 where E≠1. Here, the code word appearing in the output of the code word generation circuit 3 is assumed to be CL b. Note that in Table 3, corresponds to the data word appearing at the output of the holding circuit 1. For example, if the value of the data word is 154, the third
Table No. 154 code word 100011100111
appears in the code word generation circuit 2.

The holding circuit 4 receives the output of the code word generation circuit 2, the holding circuit 5 receives the output of the code word generation circuit 3, and the holding circuit 6 receives the parameter E regarding the R block of the immediately preceding code word CW, -th, Holds the value of LB. Note that the value of LH may be the value of the last bit of the code word CWx-start.

Further, the inversion control signal generation circuit 7 generates a value Y that controls whether or not the code word CW+a is made into a back pattern according to Table 2 (Y=1: back pattern).

Here, TB regarding the code word CW+, FlL
The values of B and E are TBl and FI LB1%, respectively.
Let it be El. In addition, the values of TBIF, LB, and E regarding the immediately preceding code word CW (1-11° are respectively T
Rl-1, FI Shizuku, LBI-+1El-1.

At this time, if the inversion information regarding the immediately preceding code word CWi1-11m is Y + -+, then code word CW1. The reversal information Y1 regarding the value becomes 1 when the following three conditions are satisfied.

(Y, 1) LBX+S=O, F+=0(Y, 2)
LBX+-+ = 0. E l-1= Ol and FI
=2(Y,3)LBX+-+=1. Et-1≠01
And FI: However, LBX+-+ is obtained by exclusive OR of LBI-1 and Y+-+.

On the other hand, the selection signal generation circuit 8 generates a selection signal S, and by switching the switch 9 using this selection signal S, the codeword from the codeword generation circuit 2 or the codeword from the codeword generation circuit 3 is selected. Choose one. This selection signal S becomes 1 only when the following conditions are satisfied, and the code word generation circuit 3
Select a codeword from .

(S, I) E number-1=0, LBX+-+≠TBI,
And, F1=1(5,2)El-+=2, LBX
+ -I: TBl, and F1=11=1Y,
As can be seen from 1) to (Y, 3), (S, l), and (S, 2), both the inversion control signal generation circuit 7 and the selection signal generation circuit 8 can be realized by simple logic circuits. next,
Parallel/serial converter lO converts the 12-bit parallel codeword appearing at the output of switch 9 into serial data. The EXOR gate 11 inverts the serial code word using the output of the parallel/serial converter IO and the inversion control signal Y from the inversion control signal generation circuit 7.
Or send it out uninverted. The holding circuit 12.13 is
It is used for time adjustment of the code word output from the parallel/serial converter 10 and the inverted control signal for this code word.

On the other hand, the synchronization pattern generation circuit 14 uses 2 words (24 bits)
The synchronization pattern of F=1. generates E=1 and counter 1
According to the synchronization pattern section signal from 5, the synchronization pattern is sent to switch 16, F to switch 17, and E to switch 18, respectively. The switch IB, 17.18 selects and outputs each signal from the synchronization pattern generation circuit 14 only while the synchronization pattern section signal from the counter 15 is ON. As a result, F=1 for the synchronization pattern
．． It is processed in exactly the same way as the E'=1 codeword, and the synchronization pattern will not be reversed and no violation of d, k restrictions will occur before or after the synchronization pattern.

As mentioned above, an 8-bit code word is converted into a 12-bit data word using the circuit configuration shown in Figure 1, and the converted 1
The number of consecutive bits of the same binary value in a bit string generated by connecting 2-bit data words can be limited to 2 or more and 10 or less. Furthermore, in the present invention, since the code word is processed in parallel until just before it is sent, the requirements for the operating speed of the circuit components are low, and in addition to the small circuit scale itself, it is extremely practical.

Next, a decoding circuit for decoding an 8-bit data word from a 12-bit code word will be explained. In conventional decoding methods, the 12 bits to be decoded are directly decoded into 8-bit data words. This decoding is performed in a ROM (Read Only
Memory), the required capacity of the ROM is 2I2X8=32 kilobits. - On the other hand, the capacity of the ROM required for the decoding circuit used in the present invention is at most 4 kilobits. The decoding method of the present invention will be explained below, and then the decoding circuit will be described in detail.

The decoding method according to the present invention is characterized by the following two points.

(1) All leading bits of the code word to be decoded are 1.

(2) Instead of decoding the code word itself, decoding is performed using a bit pattern identification code obtained by dividing the code word.

Next, we will show that correct decoding can be achieved using a decoding method with these characteristics.

As shown above, regarding the code word of the present invention with F≠1, the code word W2 starting with 1 and the back pattern 12 of the code word W2
' corresponds to the same data word.

Therefore, if it is found that F≠1 of the codeword to be decoded, whether this codeword is the codeword W2 starting with 1 or not,
Alternatively, there is no need to distinguish between the back pattern 12' of the code word W2 and decode it. From this, for codewords with F≠1, the same identification code may be associated with codewords W2 and W2'.

On the other hand, for the code word with F=1, the first bit TB is 1
The code word W2 and the back pattern W2' of the code word W2 whose TB is O are made to correspond to different data words. Therefore, the data story corresponding to the code word W2 and the code word W
2', it is necessary to output an identification code that can distinguish code words W2 and W2' from each other.

However, the data word corresponding to code word W2 and the data word D' corresponding to code word W2' are complementary, that is, all 1's of the data word are inverted to O's, and all O's are inverted.
When the data word obtained by inverting 1 to 1 is D'', the identification code for the code word W2 and the identification code for the code word W2' can be made equal.

This is because ID is the identification code for the code word W2, and D is the data word output for the identification code D. At this time, since the identification code for the code word W2' is also ID, the data word output is also D. Here, code word W2'
If it is detected that F'=1 and TB=0, all the 1's in the data story of the decoder output are inverted to 0 and all the O's are inverted to 1. By doing this,
A data word D' corresponding to the final code word W2' is obtained.

A decoding circuit configured based on the decoding method described above will be explained in detail using FIG. 5. 12 in Figure 5
Exclusive OR (EXOR) gates 19 and twelve NOT (NOT) gates 20 are for converting a 12-bit code word to be decoded into a code word that always starts with 1. For example, the code word to be decoded is I(1(111
Assume 1001100. The first bit T of this code word
Since B is 1 and EXOR gate 1B acts as a negation, the output of NOT gate 20 is 10011100110
becomes 0. Conversely, the codeword to be decoded is 01100011.
Assuming 0011, since TB:O of this code word, the input appears as is at the output of EXOR gate 1B. Therefore, the output of NOT gate 20 is 1001
11001100 is obtained.

The temporary decoding circuit 21 in FIG. 5 generates an identification code for the upper six bits of the code word that always starts with 1 and is obtained at the output of the NOT gate 20. As can be seen from Table 3, there are 13 different upper 6 bits of code words starting with 1, as shown in Table 4. Therefore, the identification hood (10) for the upper 6 bits can be represented by 4 bits. moreover,
The temporary decoding circuit 21 determines that F=1 and TB= of the code word to be decoded.
It also outputs an inverted control signal Y that becomes 1 only when the signal is O. Note that the inverted control signal Y can be realized by a simple logic circuit.

Further, the temporary decoding circuit 22 in FIG. 5 generates an identification code for the lower 6 bits of the code word obtained at the output of the NOT gate 20 and always starting with 1. As can be seen from Table 3, there are 26 ways for the lower 6 bits of a code word starting with 1 as shown in Table 5.

Therefore, the identification code (ID) for the lower 6 bits
can be expressed in 5 bits.

Tables 6.1 and 6.2 show that the 9-bit identification code thus obtained corresponds to the code word starting with 1 in Table 3 without duplication. The inverse conversion circuit 22 in FIG. 5 is for realizing Table 6, and outputs data for the 9-bit identification code in Table 4, Table 6, Table 6.1, and Table 6.2.

The eight EXOR gates 24 are the 8
This is for determining the exclusive OR with the inverted control signal Y for each bit. As shown earlier,
For a codeword with F=1, the codeword starting with 1 and the data word corresponding to its back pattern are also complementary to each other.

Therefore, for a codeword with F=1 and TB=0, Y
=1, so only in this case the output of the EXOR gate 24 becomes a value obtained by inverting the output of the inverse conversion circuit 23, and correct decoded data can be obtained.

As described above, the decoding circuit of the present invention uses an identification code for a bit pattern obtained by dividing a codeword, rather than the codeword itself, to reduce the R required for decoding.
The OM capacity has been reduced to 1/8. Specifically, the temporary decoding circuits 21 and 22 in FIG. 5 are relatively simple logic circuits (for example, programmable log
c Device).

Therefore, it is only the inverse conversion circuit 23 that is more convenient to use a ROM. The capacity required for this ROM is 2” x 8 since the address is 9 bits and the output is 8 bits.
= 4 kilobits. This is the total ROM capacity required for the decoding circuit of the present invention, and requires only 1/8 of the ROM capacity required for the conventional decoding method.

In addition, in this example, 8712, which is highly effective for high-density recording, is used.
Although the conversion code is shown as an example, any d+k, m.

It is also valid for n. In the present invention, regarding the control to satisfy the d and k restrictions, the bit length m1 of the data word is
and the bit length n of the codeword are completely irrelevant. Strictly speaking, the parameter TB1F representing the characteristics of the code word
, LB, and E alone can satisfy the d and k restrictions.

The method of determining F and E for the 8/12 conversion code conversion was shown above, and this can be converted into a film and given as follows.

E=2. (k-to'<r≦-d+1) However, d'
is the largest integer not exceeding d/2 and N k' is/
It is the largest integer not exceeding 2.

Furthermore, regarding d;1, F=01 E=O does not exist. Applying the connecting agent between code words shown earlier to the parameters F and E defined above, d,
Ensure that the k limit is satisfied.

Also, it can be realized in exactly the same way for NRZI recording, and N
Since it is an RZI record, there is nothing special about it.

Effects of the Invention The present invention directly converts an 8-bit data word into a 12-bit code word, and Tw:0. EiG7T1d =
R has a performance suitable for high-density recording of 2°k=l0.
The LL code was realized with a very practical circuit configuration. As a result, when converting the code of digital data in units of 8 bits, a code word error of one word during decoding will not expand to two words, and the decoding error rate of data words can be greatly improved compared to the conventional method. .

Moreover, generation of erroneous synchronization patterns can be completely prevented without violating the d and k restrictions, and perfect block synchronization can be achieved.

Furthermore, the new decoding method reduces the ROM capacity required for decoding to 1/8 compared to the conventional decoding method.

As described above, the present invention not only realizes an RLL code with excellent recording and reproducing characteristics, but also has the excellent feature of being extremely easy to put into practical use. Therefore, the present invention is particularly effective for digital VTRs, optical discs, etc. that require high-density recording, and in addition to being able to be realized with an extremely small circuit scale, the present invention has great practical effects.

For convenience of explanation, NRZL records are assumed and 8/12
Although the explanation has been given using an example of conversion code conversion, it goes without saying that it is also valid for NRZr recording and other (L k+ m+ n).

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a code conversion device according to an embodiment of the present invention, FIG. 2 is a structural diagram of code word 1 in the same device, and FIG.
FIG. 4 is an explanatory diagram showing connections between code words, FIG. 4 is a structural diagram of a synchronization pattern, and FIG. 5 is a block configuration diagram of a decoding circuit. 1.3-8. 12. 13...Holding circuit, 2...Code word generation circuit, 7...Inversion control signal generation circuit, 8...Selection signal generation circuit, 9.16-18...Switch, 10...
P/S, 11...EXORl 14...Synchronization pattern generation circuit, 15...Counter. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (5)

[Claims] (1) A run length method that converts an m-bit data word into an n-bit code word and limits the number of consecutive bits of the same binary value in a bit string obtained by connecting the converted code words to d or more and k or less. A code converting device that generates a limited code, comprising a code converting means in which each data word is associated with a code word group including at least one code word, and a code generated by the code converting means. A code word selection means for selecting a code word W2 from a word group, and a code word W1 immediately before the code word W2 based on the selection result of the code word W2.
a code word modifying means for modifying the selection from a code word group to which the code word belongs; a temporary decoding means for generating an identification code for each of a plurality of bit patterns obtained by dividing the code word; a code inverse converter for generating a value related to a data word corresponding to a code word; and a data word for generating a data word corresponding to the code word by modifying an output of the code inverse converter according to characteristics of the code word. A code conversion device comprising: decoding means. (2) A run length method that converts an m-bit data word into an n-bit code word and limits the number of consecutive bits of the same binary value in the bit string obtained by connecting the converted code words to d or more and k or less. A code conversion device for generating a limited code, comprising a code conversion means in which each data word is associated with a code word group including at least one code word, and an output of the code conversion means and a synchronization pattern. a switching means for switching the output of a synchronization pattern generating means for generating a synchronization pattern generating means; a code word selecting means for selecting a code word W2 from a code word group obtained from the outputs of the code converting means and the switching means; and a selection result of the code word W2. Accordingly, the code word W2
a code word modifying means for modifying the selection of the immediately preceding code word W1 from the code word group to which it belongs; a temporary decoding means for generating an identification code for each of a plurality of bit patterns obtained by dividing the code word; code inverse conversion means for generating a value related to a data word corresponding to the code word based on an identification code; and data corresponding to the code word by correcting the output of the code inverse conversion means according to the characteristics of the code word. A code conversion device comprising: data word decoding means for generating data words. (3) 1 in the code word appearing in the output of the code conversion means
When the absolute value of the difference in the number of 0 and
3. The code conversion according to claim 2, wherein one of the codewords having a DP larger than the DPmax among the codewords satisfying the k limit is outputted two consecutively, and this is used as a synchronization pattern. Device. (4) a first code word generating means for generating an n-bit code word W2a in response to an input m-bit data word; a second code word generation means for generating a word W2b, and the code word selection means combines the code word W2a with W2a in advance based on information regarding the immediately preceding code word W1 and information regarding the code word W2a. replacement signal generation means for controlling whether or not to replace the code word W2b with another code word W2a' that is currently in use or with another code word W2b' that is previously combined with W2b; a replacement control signal delay means for delaying the code word W2a based on the output of the replacement control signal delay means;
or a code word replacing means that outputs W2b as it is or replaces it with the code word W2a' or W2b', and the code word modifying means outputs the code word W2b.
2a; and a first delay means for delaying the code word W2b.
of the first delay means based on information regarding the code word of the output of the first delay means and information regarding the code word W2a of the output of the first code generation means. 4. The code conversion apparatus according to claim 1, further comprising a selection means for selecting either an output code word or an output code word of said second delay means. (5) Code word W2 starting with 1 and the 1 of said code word W2 being set to 0
, the back pattern W of the code word W2 in which all 0s are inverted to 1s.
2' correspond to different data words, the code word generation means 1 generates the code word W2 in response to the input of the m-bit data word D.
The code word W2
The code word generating means 2 generates the code word W2b in response to the input of the data word D, and the code word W2b is generated in response to the input of the data word D'.
, the code inverse converting means outputs the same value for each of the code words W2a, W2b, W2a', and W2b', and the data word decoding means generates the code inverse converting means a data word inversion control signal generating means for generating a data word inversion control signal for controlling whether to invert the output of the data word inversion control signal; and based on the data word inversion control signal,
data word selection means for selecting whether to use the output of the code inverse conversion means as it is as a data word for the code word or to invert the output of the code inverse conversion means and use it as a data word for the code word; 5. The code conversion device according to claim 4, characterized in that: