JPH0451615A - Nr 23m code conversion system - Google Patents

Abstract

PURPOSE:To reduce the scale of a circuit and to improve conversion time by providing three kinds of 2/3 conversion tables converting two data bits into three channel bits and four kinds of 4/6 conversion tables converting four data bits into six channel bits. CONSTITUTION:The three kinds of 2/3 conversion tables converting two data bits into three channel bits and the four kinds of 4/6 conversion tables converting four data bits into six channel bits are provided. Two kinds of 2/3 conversion tables and two kinds of 4/6 conversion tables are decided so that one LSB channel bit becomes the inverted code of one MSB bit of the subsequent channel bit and two kinds of conversion tables are separately used in accordance with the data bit. Then, the code is converted and NRZI recording is executed. The two kinds of the 2/3 conversion tables and the 4/6 conversion tables are stored in conversion ROM 16 and the conversion table to be used is selected in accordance with the output of a judgment circuit 14. Thus, a decoding circuit is simplified and speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an NR23M code conversion method, and particularly to a (1,7) code conversion method suitable for digital VTRs, optical disk devices, and the like.

[Conventional technology]

In general, in order to achieve high-density recording in digital VTRs, digital optical disk recording devices, etc., the minimum inversion interval Tm1n of the recording signal is made as large as possible in order to suppress code amount interference, and bit synchronization or byte synchronization is performed in a short time during playback. It is recommended that the maximum inversion interval Tmax be as small as possible to ensure synchronization, and that the detection window width Twin be as large as possible to reduce the influence of mechanical jitter, and these conditions should be achieved. The (1,7) code conversion method was developed as an encoding method for this purpose.

FIG. 7 is a circuit diagram showing an example of a conventional (1, 7> encoder).

The (1, 7) encoder 1 shown in FIG. 7 controls reading of the conversion table stored in the conversion ROM 2 by the table selection circuit 3, and converts 2-bit or 4-bit data bits into 3 bits, respectively.
/2 times the number of bits, that is, 3 bits or 6 bits.

FIG. 8 is a diagram showing an example of a code conversion table stored in the conversion ROM in FIG. 7.

According to FIG. 8, the non-sign-inverted bits "0'' that appear consecutively in the converted channel bits indicate bits whose sign is not inverted when the channel bits are NRZ I encoded, and the sign-inverted bits "0'' are not inverted when the channel bits are NRZ I encoded. This is the bit concept that is the opposite of ``. In addition, when the data bit interval is expressed as T, <1.7) The minimum sign inversion interval Tm1n of channel bits in the code conversion method is 4T/3, and the maximum sign inversion interval Tmax is 16T/3, and the detection The window width T w i n is 2T/3.

[Problem to be solved by the invention]

The previously used (1.7) code conversion method described above performs inverse conversion of channel bits/data bits from 3 to 6 channel bits to 2 to 4 data bits during playback. However, at this time, we first tried to convert the 6 channel bits into 4 data bits using a special conversion table,
If an inverse conversion pattern exists in the special conversion table, the 6 channel bits are inversely converted into 4 data bits in the special conversion table, and if the inverse conversion pattern does not exist in the special conversion table, the normal conversion table is used. Convert the 3 channel bits back to 2 data bits. Therefore, there are two types of inverse conversion: one using the special conversion table and the other using the normal conversion table.
Since this method requires a lot of time and effort, it has disadvantages in terms of algorithm complexity, circuit size, and conversion time.

[Means to solve the problem]

In the NR23M code conversion method of the present invention, the number of consecutive non-sign-inverted bits of data bits is at least 1. Convert to channel bits within the maximum range of 7 (1.7> code conversion method, 2/3 conversion table that converts 3 types of 2 data bits to 3 channel bits, and 4 types of 4 and a 4/6 conversion table for converting data bits into 6 channel bits, and two types of the 2/3 conversion tables and the 4/6 conversion table.
Two of the six conversion tables are set so that the first channel bit and the SBI bit are the inverted sign of the MSB1 bit of the next channel bit, and code conversion is performed using the two types of conversion tables depending on the data bit. TeNRZ
It is characterized by recording. In addition, the 2/3 conversion table defines a conversion rule for converting three types of data bits, 00.01 and 10, into channel bits 00X, 010, and 10X, respectively, during encoding, and the 4/6 conversion table represents four types of data bits 1100, 1101.1110, 1111 respectively as channel bit 00001
0 00000 000 becomes 11,00,01, 001 becomes 0
0.01. ], 1, 010 becomes 01.00, 10, 1
00 is inversely converted to 11.10 and 101- is inversely converted to 10, or the 2/3 conversion table is converted to 11.1 when encoding.
It defines a conversion rule for converting three types of data bits of 0.01 into channel bits 00X and 01010X, respectively, and the 4/6 conversion table is 0011,001.
Four types of data bits of 00001.0000 are converted into channel bits 000010, 00000X, 10
It defines a conversion rule for code conversion to 0010, 10000 00
,11 10,001 is 11,10.00,010
is on 10.11.01, 100 is on 00,01, 1゜1
may be inversely converted to 01, and in addition to the NR23M code, 0101001 with 16 bits of data bits and 24 bits of channel bits.
It may include a pattern that does not exist in the data section 00000001000000010, and may also include a synchronization signal so that the connection with the data section is smooth and DC-free.

[Effect]

The present invention converts 2 to 4 data bits into 3 to 6 channel bits according to a conversion table during recording, and converts 3 to 6 channel bits during playback.
After recovering the symbol synchronization from bit to 6 channel bits, 2 bits to 4 bits according to the inverse conversion table.
It reproduces the data bits of the bits, so there is no need to consider the distinction between the special conversion table and the normal conversion table when playing, just look at the 7 channel bits (3 bits + 3 bits before + 1 bit after). shows the effect that it can be converted into data bits.

〔Example〕

Next, embodiments of the present invention will be described with reference to FIGS.

FIGS. 1 and 2 are circuit configuration diagrams each showing an example of an NR23M encoder/decoder in an embodiment of the NR23M conversion method of the present invention. FIG. 3 is a diagram showing a first example of the code conversion table stored in the conversion ROM in FIG.
Figures 4 and 5 are a diagram showing a code conversion table and a code inverse conversion table when NR23M conversion is actually performed in the embodiment shown in Figure 1, respectively, and Figure 6 is a diagram showing the conversion in Figure 1. It is a figure which shows the 2nd example of the code conversion table stored in ROM.

In the NR23M encoder 11 shown in FIG. 1, 8-bit data is first latched by a latch circuit 12 consisting of a D flip-flop circuit, and the latched data is subsequently converted into serial data by a parallel/serial conversion circuit 13. . The data bits converted to serial data are judged by the judgment circuit 14 as to whether the conversion symbol is 2 bits or 4 bits, and sent to the conversion ROM 16 via the serial/parallel conversion circuit 15 in the next stage. Be talented.

As shown in FIG. 4, the conversion ROM 16 stores two types of conversion tables, a 2/3 conversion table and a 4/6 conversion table, and the conversion table to be used is determined according to the output of the determination circuit 14. selected. Judgment port Fr414 shown in this example
When the hit power is 00, 01, 10, the 2/3 conversion table is selected, and as shown in Figure 4, the conversion rule for code conversion to channel bits 001, 000.010, 101, 100 is determined. 4/6 conversion table is selected when the data bit is 1100.1101.1110.1111, and the channel bit 000010.000001.00000 as shown in FIG.
This defines a conversion rule for code conversion to 0,100010.100001 100000.

The channel bits converted from data bits in the conversion ROM 16 are first converted into serial data in a parallel/serial conversion circuit 17, and then converted from NRZ code to NRZI code in a subsequent NRZ/NRZ I conversion circuit 18. Note that a judgment circuit 14 is connected between parallel/serial conversion ports i13 and 17, and depending on the data bits, 3 bits, 6
A timely shift signal is supplied to the parallel/serial conversion circuit 17 to perform the operation of converting bits into channel bits.

Furthermore, the clock signal of the latch circuit 12 and the shift signal of the parallel/serial converter 13 may have a frequency of 1/8 of the clock signal CK of the parallel/serial converter 13 and the serial/parallel converter 15; Series conversion circuit 17 and NRZ/NRZ
Since the clock signal of the I conversion circuit 18 is required to have a frequency 1.5 times higher, care must be taken.

The decoder 21 shown in FIG. 2 performs a decoding process in the reverse order of the encoding process in the NR23M encoder 11, and is first connected to the first-stage NRZI/NRZ conversion circuit 22 via the serial/parallel conversion circuit 23. Reverse conversion ROM24
Inverse conversion is performed according to the conversion table. However,
Here, by utilizing the feature of the present invention that the decoding circuit does not require a circuit that determines how many bits the channel bits are divided into in the decoding ratio table, the decoding circuit can be simplified and increased in speed. can. That is, as shown in FIG.
This can be realized by converting a channel bit into two data bits. in this case,
As shown in FIG. 5, channel bit 000 is 11
゜00.01, 001 is 00.01,11, 010
is 01,00,10, 100 is 11.10, 101
are respectively inversely converted to 10.

A serial/parallel converter circuit 26 is connected to the inverse converter ROM 24 via a parallel/serial converter circuit 25, and data bits converted from serial data to parallel data are output via a latch circuit 27 at the final stage. Ru. Note that a determination circuit 2 is provided between the serial/parallel conversion circuit 23 and the parallel/serial conversion circuit 25.
8 is connected, and the determination circuit 28 referred to here determines whether to inversely convert 3 channel bits to 2 data bits or 6 channel bits to 4 data bits. It is not a complicated circuit, and is a simple circuit that simply generates a clock signal that extracts channel bits in units of 3 bits from a synchronization signal included in data. This judgment circuit 2
8 instructs the channel bits sent to the inverse conversion ROM 24 to be converted in units of 3 bits.

In addition, as another example, the code conversion table stored in the conversion ROM 16 may include a 2/3 conversion table and a 4/6 conversion table, as shown in FIG. 6, in addition to the code conversion table shown in FIG. Table 2
The 2/3 conversion table has 11, 10.
The three types of data bits of 01 are channel bits 001
, 000, 010.101 and 100 respectively, and the above 4/6 conversion table is 0.
Four types of data bits 011.0010,0001,0000 are converted into channel bits 000010.00000
1,000000,100010.100001 10
There is a method that uses a code conversion table that defines conversion rules for converting codes to 0000 and 0000 respectively. That is, all the data bits in the code conversion table shown in FIG. 3 are inverted.

At this time, the contents of the conversion ROM 16 and the inverse conversion ROM 24 are not shown, but the data bits of the conversion ROM 16 are all inverted in FIG. 4, and the data bits of the conversion ROM 24 are as shown in FIG. All bits are inverted.

Furthermore, as another example, there is one in which a synchronization signal is defined. The synchronization signal exists to synchronize the data in the data bits, and it must be a pattern that does not exist in the data.The connection between the preceding and succeeding data bits must be smooth.Only the synchronization signal There are conditions such as that it is preferable to be DC free, and here, 16 data bits and 24 channel bits 010100100000001000000010
Let be the synchronization signal. This synchronization signal is a pattern 10000000100000001 that does not exist in the data bits.
, and even if the data bit ends with 11, which is not a delimiter, assuming that the first data bit of the synchronization signal is 00, and converting it to a channel hit by adding 1100, the converted channel hit is 000010
This has the advantage that the last three bits of the channel bits and the first three bits of the synchronization signal are both 010 and match, and after the synchronization signal, no matter what data you start from, the channel bits will be 1 and 1. There are 1 to 7 0s between them, which does not violate the rules for the minimum inversion interval Tm1n and the maximum inversion interval Tmax, and has the advantage that it is DC-free when looking only at the synchronization signal.

〔Effect of the invention〕

As explained above, according to the present invention, when the data bits are 00.01, 10, the 2/3 conversion table is selected when the channel bits are 001.000, 010.
The code is converted to 101,100, and the data bit is 110.
Channel bits 000010, 0 select the 4/6 conversion table when 0.1101, 1110.1111
00001, 000000. 100010. 10
By converting the code to 0001.100000, the minimum inversion interval Tm1n=4T/3. ! Jt large reversal interval Tm
ax=16T/3. Detection window width T w i n = 2
This produces the effect that T/3 can be realized.

Also, during playback, channel bit 000 is 11.00.
,01, 001 is 00 01,11, 010 is 01
,00,10, ]00 is 11.10, 101 is 10
By inversely converting each to This can be realized by converting 3-bit channel bits into 2-bit data bits, which has the effect of simplifying the decoding circuit and providing high-speed performance.

Furthermore, by inverting all data bits,
The 2/3 conversion table converts the three types of data bits 11.10.01 into channel bits 001, 000.010, 101.
, 100, and the 4/6 conversion table is 0011,0010,0001,
Channel bit o
oo.

10.000001. O○0000,100010.1
A similar effect is produced by defining conversion rules for code conversion to 00001 and 100000, respectively.

Furthermore, 010100100000001000 is 16 data bits, 7 channel bits, and 24 bits.
By using 000010 as the synchronization signal, the pattern 1000000010000 that does not exist in the data bits
0001, and even if the data bit ends with 11, which is not a delimiter, the first data bit of the synchronization signal is 0.
Assuming that it is 0, and converting it to a channel bit with 1100, the channel bit after conversion is 00.
010, and has the advantage that the last three bits of the channel bits and the first three bits of the synchronization signal are both 010 and match, and after the synchronization signal, even if you start from data such as , the channel bit will not be 1. 0 is 1 between and 1
The number is greater than or equal to 7 and less than or equal to 7, does not violate the rules of minimum inversion interval Tm1n and maximum inversion interval Tmax, and furthermore, when looking only at the synchronization signal, it is DC-free and has the effect that data synchronization can be easily achieved. .

Circuit, 13, 17.25...Parallel/serial conversion circuit, 14
．． 28... Judgment circuit, 15, 23.26... Serial/parallel conversion circuit, 16... Conversion ROM, 18... NRZ
/NRZ I conversion circuit, 21 =・Decoder, 22・N
RZI/NRZ conversion circuit, 24... inverse conversion ROM.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 each show an NR2BM encoder in an embodiment of the NR23M conversion method of the present invention. FIGS. 3 and 6 are circuit configuration diagrams showing an example of a decoder, respectively. A diagram showing a second example, FIG. 4, and FIG. 5 are respectively a diagram showing a code conversion table when NR23M conversion is actually performed in the embodiment shown in FIG. 1, and a diagram showing a code inverse conversion table.
FIG. 7 is a circuit diagram showing an example of a conventional (1,7) encoder, and FIG. 8 is a diagram showing an example of a code conversion table stored in the conversion ROM in FIG.

Claims (1)

[Claims] 1. A code conversion method (1, 7) for converting data bits into channel bits by limiting the number of successive non-sign-inverted bits to a range of 1 at a minimum and 7 at a maximum, which includes three types: a 2/3 conversion table for converting 2 data bits into 3 channel bits, and a 4/6 conversion table for converting 4 types of 4 data bits into 6 channel bits; Two types of the 4/6 conversion table are determined so that the LSB 1 bit of a channel bit is the inverted sign of the MSB 1 bit of the following channel bit,
NRZ I is characterized in that code conversion is performed while using the two types of conversion tables according to the data bits, and the NRZ I recording is performed.
R23M code conversion method. 2. The above 2/3 conversion table converts three types of data bits 00, 01, and 10 into channel bits 00 and 00, respectively, during encoding.
It defines the conversion rule for code conversion to X, 010, 10X, and the 4/6 conversion table is 1100, 1101,
The four types of data bits 10 and 1111 are channel bits 000010, 00000X, and 10001, respectively.
It defines a conversion rule for code conversion to 0, 10000 11,00
, 01 to 01, 001 to 00, 01, 11, 010 to 01
, 00, 10, 100 becomes 11, 10, 101 becomes 10
2. The NR23M code conversion method according to claim 1, wherein the NR23M code conversion method performs inverse conversion. 3. The above 2/3 conversion table converts three types of data bits 11, 10, and 01 into channel bits 00 and 00 respectively during encoding.
It defines the conversion rule for code conversion to X, 010, 10X, and the 4/6 conversion table is 0011, 0010, 00
The four types of data bits 01 and 0000 are channel bits 000010, 00000X, and 10001, respectively.
0, I0000 00, 11
, 10, 001 to 11, 10, 00, 010 to 10
, 11, 01, 100 to 00, 01, 101 to 01
2. The NR23M code conversion method according to claim 1, wherein the NR23M code conversion method performs inverse conversion. 4. In addition to the NR23M code, 16 data bits
bit, channel bit 24 bits 010100
2. The NR23M code conversion method according to claim 1, wherein the NR23M code conversion method includes a pattern that does not exist in the data section of 100000001000000010, and includes a synchronization signal such that the connection with the data section is smooth and DC-free.