JPH02290334A - 2, 7 code modulation system - Google Patents

Abstract

PURPOSE:To attain quick conversion with a simple constitution by using prescribed 3/6, 4/8 conversion tables and applying the conversion in the 2, 7 code modulation in which a consecutive code noninverting bit is converted into the channel bit of 2 as minimum and 7 as maximum. CONSTITUTION:Whether the code of the leading bit of 8-bit data bits is 0 or 1 via a latch circuit 12 and a parallel/serial conversion circuit 13 is decided by a deciding circuit 14. A 3/6 conversion table in which the leading bit of a conversion ROM 16 is 0 or the like (of the same kind) and succeeding 2 bits are different, in total 3 bits are converted into 6-bit channel bits in response to the result of decision and a 4/8 conversion table in which the leading bit is 1 of the same kind different from 0 and succeeding 3 bits are different, 8 different kinds 4-bit data are converted into 8-bit channel bits are used for the purpose and the 8-bit data via a serial/parallel conversion circuit 15 are subjected to the 2, 7 code modulation. The demodulation is implemented similarly and it is not required to classify the data bits in the unit of 2, 3, 4, the decision of the input data is facilitated and quick and sure conversion is implemented with the similar constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a 2.7 code modulation system suitable for optical disk memories and the like. [Prior Art] Generally, in the optical disk 5 memory, signals are often recorded only intermittently, and it is necessary to achieve bit synchronization or byte synchronization in a short period of time during playback. Plans were made to introduce a 2,7 code modulation system. This 2,7-code modulation method was originally developed as a variable-length code conversion method for large-capacity magnetic disk drives, but it has a recording density comparable to the EFM modulation method and a clock reproduction capability comparable to the MFM modulation method. There is a history of this conversion method being adopted for optical disk memory as well. The 2.7 encoder 1 shown in FIG. 11 controls reading of a conversion table stored in a conversion ROM 2 by a table selection circuit 3, and converts 2, 3, or 4 data bits into 2, 3, or 4 data bits, respectively.
Convert to channel bits consisting of twice the number of bits. FIG. 12 shows a code conversion table stored in the conversion ROM 2. According to the conversion table, the number of non-sign inverted bits “0” that appear consecutively in converted channel bits is Including the connection part, the number ranges from a minimum of 2 to a maximum of 7, and the 2.
The name 7 comes from the circumstances during this time. Note that the non-sign inversion bit "0°" refers to a bit whose sign is not inverted when the channel bit is NRZ I encoded, and is a bit concept opposite to the sign inversion bit "1".

Note that if the bit interval of data bits is represented by T, then 2
．． The minimum code inversion interval T min of channel bits in the 7-code modulation method is 3T/2, the maximum code inversion interval T max is 8T/2, and the detection window width Tw is T/2.
It is 2. [Problems to be Solved by the Invention] In the conventional 2.7 code modulation method described above, it is necessary to first classify the data bits to be converted into units of 2 and 3.4 bits, and classification into 2 bits is difficult. Although it is possible to simply determine the first most significant bit, classification into 3 or 4 bits is
This is possible only after determining the second-order bit following the first bit. Therefore, the circuit configuration of the table selection circuit 3 that performs classification is complex, and the determination takes time, which reduces the speed of the overall conversion operation. There were problems such as difficulty in optimizing the system. [Means for Solving the Problems] The present invention solves the above problems, and allows data bits to be divided into consecutive non-sign-inverted bits of at least 2 and at most 7.
This is a 2.7 code modulation method that converts four types of 3-bit data bits into 6-bit channel bits with a relationship such that the first bit is the same and the following two bits are different. convert 3/6
Prepare a conversion table and a 4/8 conversion table for converting eight types of 4-bit data bits into 8-bit channel bits, in which the inverted bit of the first bit is both the first bit, and the following three bits are different types. The present invention is characterized in that code conversion is performed while using the two types of conversion tables depending on the type of the first bit of the data bit. [Operation] The present invention provides a 376 conversion table for converting four types of 3-bit data bits, in which the first bit is of the same type and the following two bits are of different types, into 6-bit channel bits, and an inverted bit of the first bit. Using a 478 conversion table that converts 8 types of 4-bit data bits into 8-bit channel bits, in which both are the first bit and the following 3 bits are different types, the above two bits are converted according to the type of the first bit of the data bit By performing code conversion while using different types of conversion tables, data bits are converted into channel bits while keeping the number of successive non-sign inverted bits within a range of 2 at the minimum and 7 at the maximum.

[Example] Examples of the present invention will be described below with reference to FIGS. 1 to 10.
This will be explained with reference to the figures. 1 and 2 show 2. of this invention.
FIG. 3 is a circuit diagram showing an embodiment of a 2,7 encoder and a decoder to which the 7-code modulation method is applied, and FIG. 3 is a diagram showing a code conversion table.

The 2.7 encoder 11 shown in FIG. 1 first latches 8-bit data bits in a latch circuit 12 consisting of a D flip-flop circuit, and converts the latched data into parallel data in a parallel-to-serial conversion circuit l3. Convert to . The data bits converted to parallel data are judged by the judgment circuit 14 as to whether the first bit is "O'" or "1". and sent to the conversion ROM 16.

As shown in Figure 3, the conversion ROM 1B stores two types of conversion tables, a 3/6 conversion table and a 4/8 conversion table, and the The conversion table to use is selected. The 3/6 conversion table shown in the example is
The first bit is “0” and the following two bits are different 00
Four types of data bits 0,001,010,011 are converted into channel bits 100000, 010000,00
It defines the conversion rule for code conversion to 1000,000100, and the 4/8 conversion table is 1000,1001.10 where the first bit is ゜゛1'' and the following three bits are different from each other.
10.1011, 1100.1101, 1110.11
11 8 types of data bits, channel bit 00
001000,00000100,10010000,
10001000, 10000100, 0100100
This defines a conversion rule for code conversion to 0,01000100,00100100.

The channel bits converted from data bits in the conversion ROM 2 are first converted into serial data in a parallel/serial conversion circuit 17, and then converted from NRZ code to NRZI code in a subsequent NRZ/NRZI encoding circuit 18. Note that the aforementioned judgment circuit l4 is connected between the parallel/serial conversion circuits 13 and 17, and when the first bit of the data bit is "0'", the conversion operation is performed using 6-bit parallel data as one unit. and when the first bit of the data bit is “1”, the 8-bit parallel data is
The parallel/serial conversion circuit 17 performs the conversion operation as a unit.
An appropriate shift signal is supplied to the In addition, the clock signal CK of the parallel/serial conversion circuit 13 and the parallel/serial conversion circuit 15 is
On the other hand, the clock signal of the latch circuit l2 and the shift signal of the parallel/serial conversion circuit 13 may have a frequency of 1/8, but
Care must be taken because twice the frequency is required for the Glock signal of 8.

In this way, the 2,7 encoder 11 requires a total of 12 types of data, including 4 types of data for the 3/6 conversion table and 8 types of data for the 4/8 conversion table, compared to conventional methods. A code conversion table larger than that of the 2 and 7 encoder 1 is required, but depending on the type of “O゜゛ or “1” of the first bit of the data bit, the 3/6 conversion table in the conversion ROM 1B and the 4 /
In order to convert data bits to channel bits while using 8 conversion tables, a judgment circuit 1 necessary for table selection is provided.
4 has a simple configuration, and the -f'll constant operation can be completed in a short time, so code conversion can be performed efficiently.

The decoder 21 shown in FIG. 2 uses a decoding process that is the reverse of the encoding process in the 2.7 encoder 11, and first, a serial/parallel conversion circuit 23 is added to the NRZI/NRZ encoding circuit 22 at the first stage. Reverse conversion ROM24 connected via
At , inverse conversion is performed according to the conversion table. In other words, 8-bit channel data with "0" in the 7th and 8th digits becomes 4-bit data bits, and 6-bit channel data with "0" in the 5th and 6th digits becomes 3-bit data bits. is converted back to .

A serial/parallel conversion circuit 26 is connected to the inverse conversion ROM 24 via a parallel/serial conversion circuit 25, and data bits converted from serial data to parallel data are outputted via a latch circuit 27 at the final stage. be done. Note that a determination circuit 28 is connected between the serial/parallel conversion circuit 23 and the parallel/serial conversion circuit 25, and the fifth and sixth bits of the channel bits sent to the inverse conversion ROM 24 are゛, the parallel/serial conversion circuit 25 is commanded to convert in units of 3 bits, and when the 7th and 8th bits are ``゜0゛゛, the conversion operation is performed in units of 4 bits. commands the specified conversion operation.

In the above embodiment, the code conversion table stored in the conversion ROM 16 may include the codes shown in FIG. 3, such as the code conversion table shown in FIG. 4, in addition to the code conversion table shown in FIG. It is also possible to use the data bits of the conversion table with the last bits inverted.

Furthermore, assuming that the first bit is ゛1゛゜, 111
, 110, 101, 100 data bits,
Channel bit 100000,010000,001
A 3/6 conversion table that defines a conversion rule for code conversion to either 000, 000100 without duplication, and 0111,0110.
、． 0101,0100,0011,0010,000
1.0000 8 types of data bits, channel bits 00001000, 00000100, 10010
000,10001000,10000100,010
It is also possible to use a 4/8 conversion table that converts the code to any one of 01000, 01000100, and 00100100 without duplication. That is, as in the code conversion table shown in FIG. 5, the upper two bits of the data bits in the 3/6 conversion table shown in FIG. 3 are inverted, and the upper three bits of the data bits in the 4/8 conversion table are inverted. Alternatively, as in the code conversion table shown in FIG. 6, it is also possible to use the code conversion table shown in FIG. 3, in which all the data bits are inverted.

Furthermore, in each of the above embodiments, the sign reversal probability of a channel bit, that is, the probability that a channel bit contains 1, is calculated as follows, for example, using the code conversion table shown in FIG. 3 as an example.

E1+E2+E3=0.3854 However, E1 is the probability of appearance of four types of 6-bit channel bits including one bit 1, and E1= (1/8
)X (1/3)X4. In the formula, the first 1/8 is the probability that any one of the 3 data bits that exist in 8 combinations will appear,
The next 1/3 is the probability that 1 is included in the channel bit side for 1 bit out of 3 data bits, and the last 4 is the target channel bit, that is]. 00000,010000,001000,00
Represents the total number 4 of 0100.

Further, E2 is the appearance probability of two types of channel bits including one bit 1, and is calculated as E2=(1/1 6) x (1/4)X2. In the formula, the first 1/16 is the probability that any one of the 4 data bits that exist in 16 combinations will appear, and the next 1/4 is the probability that any one of the 4 data bits will appear in 16 combinations. It is the probability that 1 is included in the channel bit side for 1 bit, and the last 2 is the target channel bit, that is, 00001000,0000
Represents the total number 2 of 0100.

Furthermore, E3 is the appearance probability of six types of channel bits including two bits of 1, and is calculated as E3= (1/1 6) x (1/2) xe. In the formula, the first 1/l6 is the probability that any one of the 4 data bits among the 16 combinations will appear, and the second 1/2 is the probability that any one of the 4 data bits will appear in 16 combinations. It is the probability that 1 is included in the channel bit side for 2 bits, and the last 6 is the target channel bit 10010000, 100010001
0000100,01001000,01000100
,00100100 represents the total number 6.

As described above, according to the code conversion tables shown in FIGS. 3 to 6, the sign reversal probability of the channel bits is at a very low level. By doing so, it is possible to increase the sign reversal probability of channel bits.

In the code conversion table shown in FIG.
01, 1.010 respectively channel bit 0001
This differs from the previous ones in that it is converted to 0000,00001000,00000100. Then, the sign reversal probability of the channel bit is expressed as El + E2 + E3 + E4 = 0.4115.

However, E1 is the appearance probability of three types of 6-bit channel bits including one bit 1, and E1 = (1/8
)X (1/3)X3. In the formula, the first 1/8 is the probability that any one of the 3 data bits that exist in 8 combinations will appear,
The next 1/3 is the probability that 1 is included in the channel bit side for 1 bit out of 3 data bits, and the last 3 is the total number 3 of the target channel bits, 100000, 010000, 001000. represent. Furthermore, E2 is the appearance probability of one type of channel bit including one bit 1, and is calculated as E2=(1/8)X(2/3)Xi. In the formula, the first 1/8 is the probability that any one of the 3 data bits among the 8 combinations will appear, and the next 2/3 is the probability that any one of the 3 data bits will appear in 8 combinations. This is the probability that 1 is included on the channel bit side for 2 bits, and the last 1 represents the number 1 of the target channel bits, that is, 100100.

Furthermore, E3 is the appearance probability of three types of channel bits including one bit 1, and is calculated as E3=(1/1 6)X(1/4)X3. In the formula, the first 1/16 is the probability that any one of the 4 data bits that exist in 16 combinations will appear, and the next 1/4 is the probability that any one of the 4 data bits will appear in 16 combinations. It is the probability that 1 is included in the channel bit for 1 bit, and the last 3 is the target channel bit, that is, 00010000,00001
00000000 1 Represents the total number 3 of 00. Furthermore, E4 is the appearance probability of five types of channel bits including two bits 1, and E4= (1/1 B) x (
1/2) is calculated as X5. During the ceremony, the first 1/16
is the probability that any one of the 4 data bits out of 16 combinations will appear, and the next 1/2 is the probability that 1 appears in the channel bit for 2 of the 4 data bits. The last 5 is the probability of inclusion, and the last 5 is the target channel bits, i.e. 100
01000,10000100,01001000,0
Represents the total number 5 of 100010000100100.

In this way, by using the code conversion table shown in FIG. 7, the sign reversal probability of channel bits can be reduced from 0.3
854 to 0.4115, and the accuracy of pit clock detection during playback can be increased accordingly.

Note that the code conversion table shown in FIG. 7 can also be changed to the code conversion table shown in FIG. 8 by inverting the last bit of the data bit. Furthermore, assuming that the first bit is "1", four types of data bits 111, 110, 101, and 100 are converted into channel bits 100,000,
A 3/6 conversion table that defines a conversion rule for code conversion to any of 010000, 001000, 100100 without duplication, and 0111,0110,0101,0100,0011
,0010,0001,0000, channel bits hooo10000,00001
000,00000100, 10001000,.
10000100, 01001000, 010
It is also possible to use a 4/8 conversion table that converts the code to either 00100 or 00100100 without duplication. That is, as in the code conversion table shown in FIG. 9, the upper two bits of the data bits in the 3/6 conversion table shown in FIG. 7 are inverted, and the upper three bits of the data bits in the 4/8 conversion table are inverted. Alternatively, as in the code conversion table shown in FIG. 10, it is also possible to use a table in which all the data bits in the code conversion table shown in FIG. 3 are inverted.

[Effects of the Invention] As explained above, the present invention performs 3/6 conversion for converting four types of 3-bit data bits, in which the first bit is of the same type and the following two bits are of different types, into 6-bit channel bits. Using a table and a 4/8 conversion table that converts eight types of 4-bit data bits into 8-bit channel bits, with the inverted bit of the first bit as the first bit and the following three bits as different types, By converting the code while using two types of conversion tables depending on the type of the first bit of the bit, data bits are converted to channel bits with the number of consecutive non-sign-inverted bits kept within the range of 2 at the minimum and 7 at the maximum. can,
As a result, it is possible to obtain channel bits in which the minimum sign inversion interval is 1.5 times the bit interval and the maximum sign inversion interval is 4 times the bit interval, and the leading bit is either “1” or “0”.
Since it is only necessary to select an appropriate conversion table according to ゜゜, there is no need for a special table selection circuit, and the time required for judgment for table selection can be shortened, making it possible to shorten the overall code conversion operation time, etc. It has excellent effects. Also, the 3/6 conversion table is 000,001,OfO,01
1, 4 types of data bits, 100 channel bits
000, 010000, 001000, 000100 without duplication, and the 4/8 conversion table is 1000, 1001, 10
10.1011,1100,1101,1110,11
11 8 types of data bits, channel bit 00
001000,00000100,10010000,
10001000, 10000100, 0100100
By defining a conversion rule that converts the code to either 0,01000100,00100100 without duplication, the last two bits of each channel bit are always assigned a non-sign inverted bit ゛0゛゜, and consecutive non-sign inverted bits are assigned. The conversion rule such that the minimum number of bits is 2 and the maximum is 7 can be observed, and at the same time, the inverse conversion from channel bits to data bits can be determined from the 00 digit at the end of the channel bits, which is an important code for variable length code conversion systems. This has the effect of making it easier to judge the length.

Also, the 3/6 conversion table is 111, 110, 101, 10
4 types of data bits of 0 and 100 channel bits
000, 010000, 001000, 000100 without duplication, and the 4/8 conversion table is 0111. ,0110.010
1,0100,0011,0010,0001,O○0
8 types of data bits of 0, channel bit ooo
o1000,00000100,1001000010
001000, 10000100, 01001000,
By defining a conversion rule for code conversion to either 01000100 or 00100100 without duplication, the same effect as above can be obtained.

Furthermore, this invention can be applied to the 4 digits listed in the 3/6 conversion table.
bit 1 from channel bit 000100 containing only one bit 1
Switch the conversion target to channel bit 100100, which contains two bits, and at the same time change one of the eight types of data bits listed in the 4/8 conversion table from channel bit 10001000, which contains two bits l, to bit 1. By switching the conversion target to channel bit 00000100, which only contains 0.3854
The sign reversal probability of the channel bit was 0.411
5, thereby producing effects such as being able to satisfactorily improve the bit clock detection accuracy during playback.

[Brief explanation of the drawing]

1 and 2 are circuit configuration diagrams showing one embodiment of a 2.7 encoder and a decoder to which the 2.7 code modulation method of the present invention is applied, and FIG. 3 is a diagram showing a code conversion table. Figures 4 to 10
The figures each show a modified example of the code conversion table shown in FIG. FIG. 11. ．． ．． 2.7 Encoder, 14. ．． ．． Judgment circuit 1B. ．．
．． Conversion ROM, 2 1. ．． ．． Decoder, 24. ．． ．． ．． Reverse conversion ROM.

Claims (5)

[Claims] (1) A 2,7 code modulation method that converts data bits into channel bits by limiting consecutive non-sign-inverted bits to a minimum of 2 and a maximum of 7, in which the first bit is of the same type and the following two bits are of the same type. A 3/8 conversion table for converting four types of 3-bit data bits that are said to be different types into 6-bit channel bits, and the inverted bit of the first bit is the first bit, and the following three bits are different types. A 4/8 conversion table is prepared to convert eight types of 4-bit data bits into 8-bit channel bits, and code conversion is performed while using the two types of conversion tables depending on the type of the first bit of the data bit. A 2,7 code modulation method characterized by: (2) The above 3/6 conversion table is 000,001,010,
4 types of data bits of 011, channel bit 1
00000,010000,001000,00010
It defines a conversion rule for code conversion to any of 0 without duplication, and the 4/8 conversion table is 1000, 1001,
1010, 1011, 1100, 1101, 1110,
The 8 types of data bits of 1111 are converted into channel bits 00001000, 00000100, 1001000.
0,10001000,10000100,01001
2. The 2,7 code modulation system according to claim 1, wherein a conversion rule is defined for code conversion to any one of 000, 01000100, and 00100100 without duplication. (3) The above 3/6 conversion table is 111, 110, 101,
100 four types of data bits, channel bit 1
00000,010000,001000,00010
0111, 0110, 0111, 0110, 0111, 0110,
0101,0100,0011,0010,0001,
The 8 types of data bits of 0000 are converted into channel bits 00001000, 00000100, 1001000.
0,10001000,10000100,01001
2. The 2,7 code modulation system according to claim 1, wherein a conversion rule is defined for code conversion to any one of 000, 01000100, and 00100100 without duplication. (4) The above 3/6 conversion table is 000,001,010,
4 types of data bits of 011, channel bit 1
00000,010000,001000,10010
It defines a conversion rule for code conversion to any of 0 without duplication, and the 4/8 conversion table is 1000, 1001,
1010, 1011, 1100, 1101, 1110,
The 8 types of data bits of 1111 are converted into channel bits 00001000, 00001000, 0000010.
0,10001000,10000100,01001
2. The 2,7 code modulation system according to claim 1, wherein a conversion rule is defined for code conversion to any one of 000, 01000100, and 00100100 without duplication. (5) The above 3/6 conversion table is 111, 110, 101,
100 four types of data bits, channel bit 1
00000,010000,001000,10010
0111, 0110, 0111, 0110, 0111, 0110,
0101,0100,0011,0010,0001,
The 8 types of data bits of 0000 are converted into channel bits 00001000, 00001000, 0000010.
0,10001000,10000100,01001
2. The 2,7 code modulation system according to claim 1, wherein a conversion rule is defined for code conversion to any one of 000, 01000100, and 00100100 without duplication.