JPS6115749U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6115749U
JPS6115749U JP10113984U JP10113984U JPS6115749U JP S6115749 U JPS6115749 U JP S6115749U JP 10113984 U JP10113984 U JP 10113984U JP 10113984 U JP10113984 U JP 10113984U JP S6115749 U JPS6115749 U JP S6115749U
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor equipment
semiconductor device
hard resin
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10113984U
Other languages
Japanese (ja)
Inventor
亮一 小林
行良 中村
猛 田中
Original Assignee
株式会社 三社電機製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社 三社電機製作所 filed Critical 株式会社 三社電機製作所
Priority to JP10113984U priority Critical patent/JPS6115749U/en
Publication of JPS6115749U publication Critical patent/JPS6115749U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の半導体装置の構造図、第2図は、この
考案の一実施例の半導体装置の構造図で・ある。 1・・・半導体チップ、2,3.5・・・リード線、7
・・・取付け板、8・・・軟質樹脂、11・・・硬質樹
脂、12,13,14・・・チューブ。
FIG. 1 is a structural diagram of a conventional semiconductor device, and FIG. 2 is a structural diagram of a semiconductor device according to an embodiment of this invention. 1... Semiconductor chip, 2, 3.5... Lead wire, 7
... Mounting plate, 8... Soft resin, 11... Hard resin, 12, 13, 14... Tube.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チップと、この半導体チップを取り付ける取付け
板と、前記半導体チップを被う軟質樹脂と、この軟質樹
脂を被う硬質樹脂により構成された半導体装置において
、硬質樹脂に接するリード線に伸縮性チューブを被覆し
た半導体装置。
In a semiconductor device composed of a semiconductor chip, a mounting plate for mounting the semiconductor chip, a soft resin covering the semiconductor chip, and a hard resin covering the soft resin, an elastic tube is attached to a lead wire in contact with the hard resin. coated semiconductor device.
JP10113984U 1984-07-03 1984-07-03 semiconductor equipment Pending JPS6115749U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10113984U JPS6115749U (en) 1984-07-03 1984-07-03 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10113984U JPS6115749U (en) 1984-07-03 1984-07-03 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6115749U true JPS6115749U (en) 1986-01-29

Family

ID=30660579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10113984U Pending JPS6115749U (en) 1984-07-03 1984-07-03 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6115749U (en)

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