JPS6115359A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6115359A JPS6115359A JP13766084A JP13766084A JPS6115359A JP S6115359 A JPS6115359 A JP S6115359A JP 13766084 A JP13766084 A JP 13766084A JP 13766084 A JP13766084 A JP 13766084A JP S6115359 A JPS6115359 A JP S6115359A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- capacitor
- thickness
- mos capacitor
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 239000003990 capacitor Substances 0.000 claims abstract description 51
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 4
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 29
- 230000008569 process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0777—Vertical bipolar transistor in combination with capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（ａｌ技術分野
この発明はＩＣ内に作成される薄膜コンデンサ特にＭＯ
Ｓコンデンサの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (al technical field) This invention relates to thin film capacitors fabricated within ICs, particularly MO
Concerning improvements to S capacitors.
ｔｂ＋従来技術とその欠点
集積回路素子上に誘電体として酸化層、電極として金属
およびシリコンを使用するＭＯＳコンデンサを形成する
場合、従来は酸化膜を一律に成長させていたために、膜
厚はＩＣ内の全てのＭＯＳコンデンサにおいて同一であ
った。一方、ＩＣの人出力ピンに直接接続されるＭＯＳ
コンデンサの酸化膜は一定の静電破壊強度を保つために
その膜厚をある程度以上薄くすることができない。しか
し、従来は全てのＭＯＳコンデンテン酸化膜の厚さが一
律であったために、素子の高密度化を阻害する原因とな
っていた。tb+Prior art and its drawbacks When forming a MOS capacitor that uses an oxide layer as a dielectric and metal and silicon as electrodes on an integrated circuit element, conventionally the oxide film was grown uniformly, so the film thickness was limited within the IC. was the same for all MOS capacitors. On the other hand, a MOS connected directly to the IC's output pin
The thickness of the oxide film of a capacitor cannot be reduced beyond a certain level in order to maintain a certain level of electrostatic breakdown strength. However, in the past, all MOS condensate oxide films had the same thickness, which hindered the ability to increase the density of devices.
（Ｃ）発明の目的
この発明の目的は上記の欠点を解消し、入出力ピンに直
接接続されるＭＯＳコンデンサの酸化膜と内路回路部に
接続されるＭＯＳコンデンサの酸化膜の厚さを変えるこ
とで素子の微細化を実現するとともに、静電破壊強度も
十分となる半導体装置を提供することにある。(C) Purpose of the Invention The purpose of this invention is to eliminate the above drawbacks and change the thickness of the oxide film of the MOS capacitor directly connected to the input/output pin and the oxide film of the MOS capacitor connected to the internal circuit section. The object of the present invention is to provide a semiconductor device that realizes miniaturization of elements and has sufficient electrostatic breakdown strength.
＋ｄ１発明の構成および効果
この発明は、ＩＣの入出力ピンに直接接続されるＭＯＳ
コンデンサの酸化膜の厚さを十分な静電破壊強度を有す
るように厚くし、内部回路部に接続すれるＭＯＳコンデ
ンサの厚さを前記入出力ピンに直接接続帯れるＭＯＳコ
ンデンサの酸化膜の■さより十分薄くしたことを特徴と
する。+d1 Configuration and Effects of the Invention This invention provides a MOS that is directly connected to the input/output pins of an IC.
The thickness of the oxide film of the capacitor is made thick enough to have sufficient electrostatic breakdown strength, and the thickness of the MOS capacitor connected to the internal circuit section is increased to the thickness of the oxide film of the MOS capacitor that can be directly connected to the input/output pin. It is characterized by being sufficiently thinner than S.A.
上記のように構成することによってこの発明によれば、
入出力ビシに直接接続されるＭＯＳコンデンサの酸化膜
の厚さが厚く、内部回路部に接続されるＭＯＳコンデン
サの酸化膜の厚さが薄いために、内部回路部のコンデン
サを微細化できるとともに、入出力ピンに接続されるＭ
ＯＳコンデンサの静電破壊強度を十分なものにできる。According to this invention, by configuring as described above,
Since the oxide film of the MOS capacitor directly connected to the input/output circuit is thick, and the oxide film of the MOS capacitor connected to the internal circuit is thin, it is possible to miniaturize the capacitor in the internal circuit. M connected to input/output pins
The electrostatic breakdown strength of the OS capacitor can be made sufficient.
また酸化膜の厚さのコントロールはホトエソチッグ工程
で容易に行うことができるため、追加する工程も簡単な
ものとなり、製造コストを大きく上昇させない利点があ
る。Furthermore, since the thickness of the oxide film can be easily controlled by the photolithography process, the additional process is simple, and there is an advantage that the manufacturing cost does not increase significantly.
ｔｅ＋実施例
第１図はこの発明に係るＩＣのウェハ断面図であり、入
出力ピンに直接接続されるＭＯＳコンデンサＣ１と内部
回路に接続されるＭＯＳコンデンサＣ２を示している。te+ Embodiment FIG. 1 is a cross-sectional view of a wafer of an IC according to the present invention, showing a MOS capacitor C1 directly connected to an input/output pin and a MOS capacitor C2 connected to an internal circuit.
図におご１て１，１′はＰ型基板、２．２′はＮ“埋め
込み層、３，３′はコレクタ型拡散によって形成される
Ｎ層、４．４′はエミッタ型拡散によって形成されるＮ
層層である。入出力ピンに直接接続されるＭＯＳコンデ
ンサＣ１はＮ４層４−酸化膜５−Ａｆｆｉ６で構成され
、内部回路に接続されるＭＯＳコンデンサＣ２はＮ４層
４′−酸化膜５′−Ａｊ！６′で構成される。各コンデ
ンサの電極は一方の電極がＮ゛層４４′であり、他方の
電極がＡｊ２６．６’である。酸化ＰＪ５，５’は上下
電極間に挟まれる誘電体として機能する。酸化膜５，５
′には一般的なＳｉＯ□や５ｉＮｎを使うことができる
。コンデンサの容量は主に酸化膜に使用する材料の比誘
電率、酸化膜の厚さ、および上下電極間で挟まれる酸化
膜の面積で決定される。 上記の構成において図示する
ように、ＭＯＳコンデンサＣ１の酸化膜５の厚さｔがＭ
ＯＳコンデンサＣ２の酸化膜５′の厚さｔ′よりも厚く
形成されている。これらの酸化膜の膜厚の制御は簡単な
工程を付加することによって行うことができる。。−例
として、まずコンデンサＣＩ、Ｃ２の両方の酸化膜を一
様な厚さに形成し、次いでコンデンサＣＩの部分をマス
クしてコンデンサＣ２に形成されている酸化膜をエツチ
ングし、続いてコンチン′１ＩＣ１，Ｃ２のコンデンサ
部に酸化膜を成長または堆積させる。これによって、内
部回路のＭＯＳコンデンサの酸化膜の厚さを入出力ピン
に接続されるＭＯＳコンデンサの酸化膜の厚さよりも十
分に薄くすることができる。尚、酸化膜の厚さの薄いＭ
ＯＳコンデンサの容量は、酸化膜の厚さかＩＮいＭＯＳ
コンデンサに比べそ他の条件が同しであるとした場合、
容量が大きくなることは言うまでもない。したがって、
第１図において、コンデンサＣ１とＣ２の容量が同しで
あるとした場合、コンデンサｃ２が占める面積をコンデ
ンサＣ１が占める面積よりも小さくすることができる。In the figure, 1 and 1' are P-type substrates, 2.2' is an N" buried layer, 3 and 3' are N layers formed by collector type diffusion, and 4.4' is formed by emitter type diffusion. N
It is layered. The MOS capacitor C1 directly connected to the input/output pin is composed of N4 layer 4-oxide film 5-Affi6, and the MOS capacitor C2 connected to the internal circuit is composed of N4 layer 4'-oxide film 5'-Aj! Consists of 6'. One electrode of each capacitor is N' layer 44', and the other electrode is Aj26.6'. Oxidized PJ5, 5' functions as a dielectric material sandwiched between the upper and lower electrodes. Oxide film 5, 5
' can be made of general SiO□ or 5iNn. The capacitance of a capacitor is mainly determined by the dielectric constant of the material used for the oxide film, the thickness of the oxide film, and the area of the oxide film sandwiched between the upper and lower electrodes. As shown in the above configuration, the thickness t of the oxide film 5 of the MOS capacitor C1 is M
It is formed thicker than the thickness t' of the oxide film 5' of the OS capacitor C2. The thickness of these oxide films can be controlled by adding a simple process. . - As an example, first form the oxide films of both capacitors CI and C2 to a uniform thickness, then mask the part of capacitor CI and etch the oxide film formed on capacitor C2, and then etch the oxide film formed on capacitor C2. An oxide film is grown or deposited on the capacitor portions of 1IC1 and C2. Thereby, the thickness of the oxide film of the MOS capacitor in the internal circuit can be made sufficiently thinner than the thickness of the oxide film of the MOS capacitor connected to the input/output pin. In addition, M with a thin oxide film
The capacitance of the OS capacitor depends on the thickness of the oxide film or the IN MOS
Compared to a capacitor, assuming other conditions are the same,
Needless to say, the capacity increases. therefore,
In FIG. 1, if capacitors C1 and C2 have the same capacitance, the area occupied by capacitor c2 can be made smaller than the area occupied by capacitor C1.
即ち、内部回路に接続されるコンデンサを微細化でき、
その分ＩＣの高密度化を実現できることになる。In other words, the capacitors connected to the internal circuit can be miniaturized,
Accordingly, higher density IC can be realized.
第１図はこの発明に係る■ｃのウェハ断面図、第２図は
同ＩＣの回路の一部を示す図である。
Ｃ１−人出力ピンに接続されるＭＯＳコンデンサ、Ｃ２
−内部回路に接続されるＭＯＳコンデンサ、５．５′−
酸化膜。FIG. 1 is a cross-sectional view of a wafer 1c according to the present invention, and FIG. 2 is a diagram showing a part of the circuit of the same IC. C1 - MOS capacitor connected to human output pin, C2
-MOS capacitor connected to internal circuit, 5.5'-
Oxide film.
Claims (1)
ンサの酸化膜の厚さを十分な静電破壊強度を有するよう
に厚くし、内部回路部に接続されるＭＯＳコンデンサの
厚さを前記入出力ピンに直接接続されるＭＯＳコンデン
サの酸化膜の厚さより十分薄くしたことを特徴とする半
導体装置。(1) Increase the thickness of the oxide film of the MOS capacitor directly connected to the input/output pin of the IC to have sufficient electrostatic breakdown strength, and enter the thickness of the MOS capacitor connected to the internal circuit section above. A semiconductor device characterized in that the thickness is sufficiently thinner than the thickness of an oxide film of a MOS capacitor directly connected to an output pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13766084A JPS6115359A (en) | 1984-07-02 | 1984-07-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13766084A JPS6115359A (en) | 1984-07-02 | 1984-07-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6115359A true JPS6115359A (en) | 1986-01-23 |
Family
ID=15203834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13766084A Pending JPS6115359A (en) | 1984-07-02 | 1984-07-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6115359A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255262A (en) * | 1988-04-05 | 1989-10-12 | Toshiba Corp | Mos capacitor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51104276A (en) * | 1975-03-12 | 1976-09-14 | Hitachi Ltd | HANDOTAISH USEKAIRO |
| JPS5693359A (en) * | 1979-12-26 | 1981-07-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit and manufacture |
| JPS57132354A (en) * | 1981-02-09 | 1982-08-16 | Mitsubishi Electric Corp | Semiconductor memory storage |
-
1984
- 1984-07-02 JP JP13766084A patent/JPS6115359A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51104276A (en) * | 1975-03-12 | 1976-09-14 | Hitachi Ltd | HANDOTAISH USEKAIRO |
| JPS5693359A (en) * | 1979-12-26 | 1981-07-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit and manufacture |
| JPS57132354A (en) * | 1981-02-09 | 1982-08-16 | Mitsubishi Electric Corp | Semiconductor memory storage |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255262A (en) * | 1988-04-05 | 1989-10-12 | Toshiba Corp | Mos capacitor |
| JPH0580153B2 (en) * | 1988-04-05 | 1993-11-08 | Tokyo Shibaura Electric Co |
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