JPH01255262A - Mos capacitor - Google Patents

Abstract

PURPOSE:To obtain a MOS capacitor which can suppress a noise by forming a second impurity layer containing high concentration impurity on a first impurity layer facing an electrode layer through an insulating film. CONSTITUTION:In a MOS capacitor having a first impurity layer 2 formed on a semiconductor substrate 1, an insulating film 3 formed on the layer 2, and an electrode layer 4 formed on the film 3, a second impurity layer 11 containing further high concentration impurity is formed on the surface layer of the layer 2. For example, a P<+> type impurity region 11 is provided on the surface layer of the P-type impurity region 2. The region 11 becomes a lower resistance layer than the region 2. Thus, since the low resistance layer becomes one electrode facing a polysilicon electrode 4, the potential of the region 11 can be stabilized through an aluminium wiring layer 8, thereby suppressing a noise.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to MOS capacitors.

(Prior Art) A cross-sectional structure of a conventional MOS capacitor is shown in FIG. A P-type impurity region 2 is formed in the silicon substrate 1, and a silicon oxide film 3 is formed on the surfaces of the silicon substrate 1 and the P-type impurity region 2. A polysilicon Flit 4 is formed on this silicon oxide film 3, and a capacitor is formed by the silicon oxide film 3 as an insulating layer, the P-type impurity region 2 and the polysilicon electrode 4 sandwiching it. A protective layer 5 is formed on the polysilicon electrode 4, and a contact hole is opened in the protective layer 5 to provide wiring. Wiring for P type impurity region 2 is conducted for P+ impurity region 6. That is, the aluminum wiring layer 8 is connected to P+ via the contact hole 7.
Connected to impurity region 6. P+ impurity region 6 is a region with higher impurity concentration than P-type impurity region 2, and serves to reduce contact resistance. On the other hand, an aluminum wiring layer 10 is connected to the polysilicon electrode 4 via a contact hole 9. In this way, aluminum wiring layers 8 and 10 become picture electrodes of a MOS capacitor.

FIG. 4 is a top view of this conventional MOS capacitor.

Each part is given the same reference numeral as in FIG. 3, and a description thereof will be omitted.

In addition, in order to make the figure clear, each part is drawn with various lines. Further, the hatched portion indicates the opening of the contact hole.

(Problems to be Solved by the Invention) However, various circuit regions are generally formed on the silicon substrate 1, and potential fluctuations occur in the silicon substrate 1 due to the operation of these circuit regions. This potential fluctuation appears in the P-type impurity region 2 as a noise component. Since the P-type impurity region 2 has a high resistance, it is difficult to suppress noise generation by stabilizing the voltage of the aluminum wiring layer 8.

Furthermore, if another circuit is formed within the P-type impurity region 2 and the P-type impurity region 2 itself is grounded, noise will also be generated by the operation of this circuit.

Therefore, an object of the present invention is to provide a MOS capacitor that can suppress the generation of noise.

[Structure of the invention]

(Means for Solving the Problems) The present invention includes a first impurity layer formed on a semiconductor substrate, an insulating film formed on the first impurity layer, and an insulating film formed on the insulating film. In this MOS capacitor, a second impurity layer containing an impurity at a higher concentration is formed on the surface layer of the first impurity layer.

(Function) The second impurity layer has a lower resistance than the first impurity layer. Since this low resistance layer serves as one electrode of the capacitor, potential fluctuations occurring within the first impurity layer can be efficiently suppressed.

(Example) The present invention will be described below based on an illustrative example. FIG. 1 is a cross-sectional structural diagram of a MOS capacitor according to an embodiment of the present invention. Here, the same components as those of the conventional MOS capacitor shown in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. The difference from the conventional MOS capacitor shown in FIG.
This is the point where 1 was set. This P+ impurity region 11 is a region having a higher impurity concentration than the P-type impurity region 2, and becomes a layer having a lower resistance than the P-type impurity region 2. Since such a low resistance layer becomes one electrode facing the polysilicon electrode 4, P+
The potential of impurity region 11 can be stabilized, and noise generation can be suppressed. Even in the case where another circuit is formed in the P-type impurity region 2, the P-type impurity region 1
1 can reduce the noise generated by the circuit.

Note that P+ impurity region 1 is formed only in the surface layer of P-type impurity region 2.
1 is formed because if other circuit elements are also formed in the P-type impurity region, the concentration cannot be made high enough. Furthermore, by forming the two-layer structure of the P-type impurity region 2 and the P-type impurity region 11, the depletion layer between the P-type impurity region 2 and the silicon substrate 1 is expanded, and the noise in the P-type impurity region 2 is There is also the advantage that it is less likely to be transmitted to the substrate 1. Further, even if a depletion layer is formed under the polysilicon electrode 4, the extension of this depletion layer is suppressed by the P+ impurity region 11, so that the capacitance as a capacitor can be prevented from decreasing.

FIG. 2 is a top view of an embodiment in which the present invention can be implemented more effectively. Here, the same components as those in FIG. 1 are given the same reference numerals, and the description thereof will be omitted. As described above, the P+ impurity region 11 and the P type impurity region 2 are
It is connected to the aluminum wiring layer 8 via the positive impurity region 6, and in this embodiment, a contact hole 7 (indicated by hatching in the figure) for this connection is made very wide. That is, the contact hole 7a is formed so as to surround the outer periphery of the polysilicon electrode 4, and
A notch is provided in the polysilicon electrode 4, and a contact hole 7b is formed in this notch. In this way, by making the contact hole 7 wider, the noise suppression effect can be further improved. Note that FIG. 2 is shown as an example, and any arrangement may be used as long as the contact hole portions can be distributed as widely as possible.

〔Effect of the invention〕

As described above, according to the present invention, in the MOS capacitor, a region with a higher impurity concentration is formed in the surface layer of the impurity layer in the semiconductor substrate, so that the generation of noise can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of a MOS capacitor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a MOS capacitor according to another embodiment of the present invention.
A top view of the capacitor, FIG. 3 is a cross-sectional structural diagram of a conventional MOS capacitor, and FIG. 4 is a top view of a conventional MOS capacitor. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... P-type impurity region, 3...
・・Silicon oxide film, 4・Polysilicon electrode, 5・
...Protective layer, 6...P impurity region, 7... Contact hole, 8... Aluminum wiring layer, 9... Contact hole, 10... Aluminum wiring layer, 11
...P+ impurity region. Applicant's agent Mr. Sato - Volume 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A first impurity layer formed on a semiconductor substrate, an insulating film formed on the first impurity layer, and an electrode layer formed on the insulating film. 1. A MOS capacitor comprising: a second impurity layer containing an impurity at a higher concentration on a surface layer of the first impurity layer. 2. Claim 1, characterized in that the connection between the first and second impurity layers and an external wiring layer is made in a peripheral portion of the electrode layer and/or a cutout portion provided in the electrode layer. MOS capacitor described in .