JPH0369151A - Mos type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor circuit element formation region and miniaturize the external shape of a device for forming 1 charge storage region consisting of a polycrystalline silicon film which is sandwiched by two oxide films so that the surroundings of the semiconductor circuit element formation region are encircled by the above storage region. CONSTITUTION:This device is composed of: a semiconductor circuit element formation region 2 equipped with a logic circuit element consisting of MOS transistors that are formed on a semiconductor board; a charge storage region 1 consisting of a polycrystalline silicon film sandwiched by two oxide films so that the surroundings of the above region 2 are encircled by the above storage region. For example, a plurality of regions are formed by arranging a grounding potential region 4 as well as each logic element region 3 that is made up by the MOS transistors on a monoconductive semiconductor board and a semiconductor circuit element formation region 2 is constructed. Further, bonding pads 5 that are input/output terminals are formed at the periphery of the above region 2 and the charge storage region 1 is formed continuously so that its region 1 surrounds the outer circumference of the above region 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a MOS type semiconductor integrated circuit device having a charge storage region.

[Conventional technology]

FIG. 4 is a plan view of a semiconductor chip showing an example of a conventional MOS type semiconductor integrated circuit device. Conventionally, that type of MOS
For example, as shown in FIG. 4, a type semiconductor integrated circuit device has a plurality of ground potential regions 4 and logic element regions 3 each composed of a MOS (MOS) transistor arranged side by side on a -conductivity type semiconductor substrate. This constituted a semiconductor circuit element forming region 2. Furthermore, a bonding pad 5, which is an input/output terminal, is formed around the semiconductor circuit element forming region 2, and a first oxide film on the semiconductor substrate and a polycrystalline film formed thereon are also formed around the semiconductor circuit element forming region 2. Charge storage regions 1a made of a silicon film and a second oxide film on the polycrystalline silicon film were formed dispersedly within the semiconductor element formation region.

[Problem to be solved by the invention]

The above-described conventional MOS type semiconductor integrated circuit device has a drawback that the area of the MOS type semiconductor integrated circuit device cannot be reduced because the charge storage region is formed only within the semiconductor circuit element formation region.

An object of the present invention is to provide a MOS type semiconductor integrated circuit device that eliminates such drawbacks.

[Means to solve the problem]

The MOS type semiconductor integrated circuit device of the present invention includes a semiconductor circuit element formation region having a logic circuit element made of a MOS transistor formed on a semiconductor substrate, and a semiconductor circuit element formation region formed so as to surround the semiconductor circuit element formation region. It has a charge storage region made of a polycrystalline silicon film sandwiched between two oxide films.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 is a plan view of a semiconductor chip showing an embodiment of the MOS type semiconductor integrated circuit device of the present invention; FIG. 2 is a partially enlarged plan view showing part A of the semiconductor chip in FIG. 1; 3
The figure is a BB sectional view of FIG. 2. In this MOS type semiconductor integrated circuit device, as shown in FIG. 1, a charge storage region 1 is continuously formed so as to surround the outer periphery of a semiconductor circuit element forming region 2. As shown in FIG. Other than that, it is the same as the conventional example. That is, as shown in FIGS. 2 and 3, this charge storage region 1 consists of a semiconductor substrate 6, a first oxide film 11 provided on the semiconductor substrate 6, and a multilayer film provided on the first oxide film 11. A second layer provided on the crystalline silicon film 7 and the polycrystalline silicon film 7
It is formed into a MOS structure consisting of an oxide film 12. Further, as described above, the conventional charge storage region 1a in FIG.
is formed around the semiconductor circuit element formation region 2, so that the semiconductor circuit element formation region 2 becomes a logic element region 3 of opposite conductivity type for operating a MOS type semiconductor integrated circuit device.
The area used as the charge storage region 1 formed in the semiconductor circuit element formation region 2 described above is deleted,
The area of the semiconductor circuit element region can be reduced, and the overall area of the MOS type semiconductor integrated circuit device can be reduced. Further, since there is no charge storage region in the semiconductor circuit element forming region, there is an advantage that there is no adverse effect on the logic circuit element due to a potential rise in the ground potential region or a potential drop in the ground potential region.

〔Effect of the invention〕

As explained above, in the present invention, the charge storage region formed within the semiconductor circuit element formation region is formed outside the semiconductor circuit element formation region to be used as a charge storage portion within the semiconductor integrated circuit element. This has the effect that a semiconductor integrated circuit device can be obtained in which the area can be reduced, the area of the semiconductor circuit element formation region can be reduced, and the external size can be reduced.

Film, 11... first oxide film, 12... second oxide film.

Claims (1)

[Claims] A polycrystalline silicon sandwiched between a semiconductor circuit element formation region having a logic circuit element made of a MOS transistor formed on a semiconductor substrate, and a two-layer oxide film formed so as to surround this semiconductor circuit element formation region. 1. A MOS type semiconductor integrated circuit device comprising a charge storage region consisting of a film and a charge storage region.