JPS6115350A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit cracks and the like of a PSG by a method wherein a wiring layer is split into a plurality of N current paths of the same length parallel at the connection part, and the width of the current path is set at the 1/N of the case of non-split wiring layer. CONSTITUTION:An impurity diffused region 12 and a field insulation film 14 made of SiO2 or the like are formed on the surface of a semiconductor substrate 10. After a contact hole to the region 12 is provided in the film 4, Al is adhered and the first wiring layer 16 having five parallel current paths 16a-16e is formed by patterning this Al film. Besides, the width of these current paths 16a-16e is: a width = Ws/5 when a wiring width of Ws is necessary as a single wiring layer, and connection parts C1 and C2 are connected to each other with five current paths 16a-16e having the same length L.

Description

Detailed Description of the Invention [Field of Sedentary Application] The present invention relates to a semiconductor device such as an RC (integrated circuit) device having fine wiring. The manufacturing yield and reliability are improved by forming a pattern having parallel current path portions.

[Conventional technology]

Conventionally, wiring layers made of Al or Al-based alloys (for example, IJ-Si alloys) have been widely used in (C devices, etc.), but all of them have been single, undivided wiring layers. Points to be solved by the invention] According to the inventor's research, it has been found that the above-mentioned prior art has the following problems.

(1) When a phosphosilicate glass (PSG) film is deposited on a wiring layer made of Al or AJ-based alloy by YCVD (chemical vapor deposition), cranks may occur in the PSG film. , Such a rack is likely to occur in #1 where the width of the wiring layer is large.

(If an SG film is deposited as described above on a wiring layer made of 21kl or an Al-based alloy, or a silicon nitride film is deposited by plasma CVD, the wiring layer will have a "hero" In this way, the wiring layer grows larger as the width of the wiring layer increases.

(Al or Al-based alloy during 311C operation,
Electromigration may occur in wiring layers that are large enough to be larger than the brain size, but such electromigration is less likely to occur as the width of the wiring layer is larger than the brain size. When it comes to a certain degree, the larger the width of the wiring layer, the more likely it is to occur.

As described above, rack generation and hillock growth reduce the manufacturing yield of the device, and electromigration reduces the reliability of the device. Therefore,
In order to improve manufacturing yield and reliability, it is possible to reduce the wiring width, but wiring #! Width is determined by taking current density, wiring resistance, etc. into consideration, so in IC devices that handle large currents, it is necessary to have a large wiring width, and the above El) to (3). It has been difficult to avoid the inconvenience caused by such a large wiring width.

[Means for solving problem A2] This invention was made to solve the above-mentioned problems, and is made by providing a wiring layer made of A7 or an A7-based alloy on an insulating film covering a semiconductor substrate. In a semiconductor device, one parallel to each other between the contact parts through which the wiring layer chemical flow flows.
The width of each current path is determined by dividing the wiring into a plurality of N current path portions having the same length, and the width of each current path portion is the wiring width required when the wiring layer is made into a single undivided wiring layer. No. 1
/N.

[Effect]

If a wiring layer of width WS is required, WS/N is
By creating multiple parallel divided wirings with the same width, it is possible to suppress the occurrence of the aforementioned cracks, hillocks, electromigration, etc. that occur due to the large wiring width, thereby improving manufacturing yield and reliability. I can do it. ,, Also, the width of each current path portion is Ws/N
Therefore, by making the spacing between current path parts as unconscionable as the processing limit of photolithography technology, the increase in overall wiring width can be minimized compared to the case of using a single undivided wiring layer. Therefore, it is possible to substantially avoid hindering the miniaturization of wiring (increasing the wiring space). The reason why the plurality of current path portions are made to have the same length t and the same width is to prevent the current distribution from becoming non-uniform and shortening the wiring life.

〔Example〕

FIG. 1 (al and (bl) show a wiring structure according to an embodiment of the present invention.

An impurity diffusion region 12 is provided on the surface of the semiconductor substrate 10 for forming circuit elements such as transistors. 1. On the surface of the substrate 100, a field insulating film 14 made of 5i02 or the like is formed.

After forming a contact hole in the insulating film 14 to expose a portion of the diffusion region 12, for example, Ad is formed on the entire surface of the substrate.
Depends on how you wear it. Then, by patterning the deposited Al film according to the first layer wiring pattern as shown in FIG. A wiring layer 16 is formed. In FIG. 1(a), C1 indicates a contact portion χ between the wiring layer 16 and the diffusion region 12.

Thereafter, an interlayer insulating film 18 is formed on the upper surface of the substrate, and then a contact hole corresponding to the contact portion C2 is provided in the insulating film 18.

Then, in the same manner as the first layer, the second wiring layer 20
Formation 1-ru. Note that for the insulating films 18 and 12, a PSG film formed by a CVD method, a silicon nitride film formed by a plasma CVD method, or the like can be used.

FIG. 2 shows the conventional first-layer wiring pattern in comparison with the wiring layer 16, where 16' is the ``first wiring layer'', 01
' and C2' are contact parts 1- That is, in the past, the wiring layer 16' was formed as a single undivided wiring layer between the contact parts C and/or C2' through which current flows. As an example, the wiring width Ws was 100 [μm].

As a result, as mentioned above, cranks were generated in the K PSG film and hillocks were grown in the A7 wiring layer 16'.

According to the embodiment of the present invention, when a wiring width of 100 [μm] is required for a single wiring layer 16', wiring layer 1
Reference numeral 6 denotes five parallel current path portions 16 which are parallel to each other and have the same length L between the contact portion through which the current flows and C2'.
The current path portion is divided and formed so that the current path portion has a width W of WS152A [μm].

The interval between the twisted and adjacent current path portions is set to about the processing limit of photolithography technology (for example, 1 [μm]).

In this way, the occurrence of PSG cracks and hillock growth in the previous stage are reduced compared to the case shown in FIG. 2, and the current capacitance, wiring space, etc. become almost the same as in the case shown in FIG.

As another example, in order to reduce electromigration defects, it is better to form a wiring layer having two current path portions with a width of 2 [μm] than to remove a single wiring layer with a width of 4 [μm]. It turned out to be good.

In other words, the wiring width is 1 in the wiring layer made of Al-8 layer alloy.
When we investigated the strength against electromigration as 0 [μm], 4 [: μm), and 2 [μm], we found that the resistance to electromigration was 4 [μm].
The one with a width of [μm] was the weakest, the one with a width of 3 [μm] of 10 [μm] was the second strongest, and the one with a width of 2 [μm] was the strongest.

Therefore, it is possible to realize a wire that is more resistant to electromigration by forming two magnolia rows of wires each having a width of 2 [μm] than a single wire having a width of 4 [μm].

In the above embodiment, A, 1 and Al-8 are used as wiring materials.
Although the layer alloys are illustrated, A7-Cu, fiJ-T
The present invention can also be applied when using I as a wiring material.

〔Effect of the invention〕

As described above, according to the present invention, a wiring layer is formed by dividing it into a plurality of N current path portions that are parallel to each other and have the same length between contact portions through which current flows, and each current path portion is Since the width is set to l/N of the required wiring width when the wiring layer is a single undivided wiring layer, the following ambiguous effects are obtained: (1) The wiring width is The PSG crank is caused by its large size.
Hillock growth and electromigration of A7 or M-based alloys are suppressed, and manufacturing yield and conformability are improved.

(2) Width of each current path section - 1/N of the width required for wiring
Therefore, it is possible to substantially avoid the problem of hindering the miniaturization of wiring.

(3) Since the plurality of current path portions have the same length and width, shortening of the wiring life can be prevented.

Brief explanation of the drawings 1 Figures 1(a) and 1(b) show a wiring structure according to an embodiment of the present invention, where (a) is a ten-sided diagram of the first layer wiring;
bl is a cross-sectional view of the board, and mj: 2 is a plan view showing a conventional wiring pattern 7.

10... Semiconductor substrate, 1/l, 18... Insulating film, 16.16'.

Addition... Wiring layer, 16a to 168... Current path portion, C
,,c1'.

C2, C2'...Contact portion.

Claims (1)

[Claims] In a semiconductor device in which a wiring layer made of aluminum or an aluminum-based alloy is provided on an insulating film covering a semiconductor substrate, a plurality of N current path portions parallel to each other and having the same length are provided between contact portions through which current flows through the wiring layer. A semiconductor characterized in that the semiconductor is formed by dividing the wiring layer so that the wiring layer has a single undivided wiring layer, and the width of each current path portion is set to 1/N of the wiring width required when the wiring layer is a single undivided wiring layer. Device.