JPS61152078A - Schottky gate type fet - Google Patents

Abstract

PURPOSE:To reduce effectively the short channel effect caused by shortening of gate by installing the buried region of inverse conduction type to the source region and the drain region in the position which is close to the channel region in the source/drain region and deeper than the position of the channel region. CONSTITUTION:The N<+> type source region 4 and the N<+> type drain region 5 are formed on bath sides of the channel region 3 directly under the gate electrode 2. These source region 4 and drain region 5 can be formed by the ion injection, but the larger injection energy is applied than that of the formation of the channel region 3. The P type buried region 6 is formed in the place which is close to the channel region in the N<+> type regions 4 and 5 and deeper than the channel region 3. This P type buried region is formed also by the ion injection and Zn or Be, for example, is applied to the ion for injection. Thus the high impurity density region of source and drain can be separated by the P-N junction, so that the leak current through the substrate can be extremely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a Schottky gate FET (MESFET) suitable for high speed and high integration.

The present invention relates to techniques effective in reducing short channel effects.

[Background Art] MESFET is known as an element structure suitable for integration of gallium arsenide (GaAs). In order to increase the speed of this MESFET, shortening the gate is effective.

However, as gates become shorter, the problem of so-called short channel effect arises, which is deterioration of device characteristics such as a decrease in mutual conductance. As a conventional technique for reducing the short channel effect, a method is known in which N4'' type high concentration layers forming the source and drain regions are formed shallowly.
s Self Line (SAINT) MESFET, see IEICE Technical Report 5S-D, 82-128, p51-56).

The inventor of the present invention has conducted various studies on such short channel effects and techniques for reducing them, and has discovered the following. That is, for one thing, the short channel effect is
This is caused by electric field concentration occurring at the edge portion of the N+ type high concentration layer located on the gate side, which causes a leakage current to flow into the substrate, and also because the high concentration layer is formed shallowly. Although this is effective in reducing the short channel effect, making it shallower reduces the ohmic contact resistance of the source and drain electrodes, increases the parasitic resistance due to the decrease in sheet resistance of the source and drain regions, and reduces the withstand voltage due to leakage from the gate. This is because there is a risk of a decline.

[Object of the Invention] An object of the present invention is to provide a technique for reducing the short channel effect without fear of voltage deterioration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention A brief outline of typical inventions disclosed in this application is as follows.

In order to prevent the deterioration of the contact resistance, sheet resistance, and breakdown voltage, it is effective to form deeply the highly doped layers forming the source and drain. So 5. These high concentration layers are formed deep.

A buried region of a conductivity type opposite to that of the source and drain is formed in a portion of each of the source and drain regions close to the channel region and deeper than the channel region. Therefore, the source and drain can be separated by the PN junction, the leakage current through the substrate can be made very small, and the short channel effect can be effectively reduced.

[Example] Figure 1 shows an ME of GaAsLS■, which is an example of the present invention.
FIG. 3 is a cross-sectional structural diagram of an SFET portion.

On one side of the semi-insulating substrate 1 made of G.a.A.s.

A gate electrode 2 made of tungsten is formed.

This gate electrode 2 is formed by known sputtering and photoetching or lift-off techniques.

Ions of silicon, tin, selenium, etc. are implanted in advance into the surface layer portion of the substrate 1 where the gate electrode 2 is located, and an N-type channel region 3 is formed. The channel region 3 is formed to be relatively shallow by controlling the implantation energy.

On both sides of the channel region 3 directly under the gate electrode 2, N+
Type source and drain regions 4.5 are formed. These source and drain regions 4 and 5 can also be formed by ion implantation, but the implantation energy is set higher than when forming the channel region 3. This is because, as mentioned above, in order to prevent deterioration in contact resistance, sheet resistance, and leakage from the gate, each of the source and drain regions 4 and 5 should be formed deeper than the channel region 3. Specifically, this is because the impurity concentration peak needs to be formed deeper than the peak portion of the channel region 3. Note that when forming each of these regions 4 and 5, the gate electrode 2 and a photoresist (not shown) can be used as a mask for ion implantation.

Two, in each of these N type regions 4 and 5, a P type buried region 6 is formed in a portion close to the channel region 3 and at a position deeper than the channel region 3.

The P-type buried region 6 is also formed by ion implantation technology, and the ions to be implanted include, for example, Zn (zinc).
Alternatively, Be (beryllium) or the like is used. Of course, this selective ion implantation can be performed by using, for example, a photoresist as a mask and appropriately controlling the implantation energy. Note that reference numerals 7 and 8 are source electrodes and drain electrodes that are in ohmic contact with the source and drain regions 4 and 5, respectively.

[Effect] In the source and drain regions, in a portion close to the channel region side and deeper than the channel region,
Since there is a buried region of the opposite conductivity type to those regions, there is a PN between the high concentration impurity regions of the source and drain.
They can be separated by bonding, and leakage current through the substrate can be significantly reduced. therefore,
The short channel effect accompanying the short gate can be effectively reduced.

In addition, since the source and drain regions are formed deeper than the channel region, it is possible to effectively prevent contact resistance deterioration, sheet resistance deterioration, and leakage from the gate, thereby reducing parasitic resistance breakdown voltage. This is a preferable device structure in terms of aspects as well.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without getting across the gist of the invention. For example, gate electrode 2
The semi-insulating substrate 1 can be formed of a heat-resistant pure metal other than tungsten or an alloy such as silicide, and the semi-insulating substrate 1 can be formed of a GaAs substrate,
Other compound semiconductor substrates can also be used.

[Field of Application] The present invention can be widely used as a technique for reducing short channel effects in MESFETs.

In particular, Ga with a gate length of 1 to 2 μm or less
Great effects can be obtained by applying it to ASLS I.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A gate electrode formed on one surface of a semi-insulating substrate, source and drain regions formed on both sides of the gate electrode containing a high concentration of first conductivity type impurities, and a channel region located between each region and containing a first conductivity type impurity at a low concentration;
In the Schottky gate FET, in which the source and drain regions are formed deeper on one surface of the semi-insulating substrate than the channel region, the source and drain regions are close to the channel region side. 1. A Schottky gate type FET comprising a buried region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, at a position deeper than the channel region.