JPH1154526A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a high-speed performance by suppressing the short channel effect which a caused when a gate length is made short, and decreasing the gate capacitance. SOLUTION: In a semiconductor substrate 1 lower than an n-type active layer 3, a p-type embedded p layer 2b is formed in contact with the n-type active layer 3. A p-type embedded p layer 2a is formed along the boundary of an n' layer 5 so as to overlap with a part of the embedded p layer 2b. A p-type embedded p layer 2c is formed along the boundary of an n' layer 6 so as to overlap with a part of the embedded p layer 26. Furthermore, when the active layer 3 is made to be the p type, the conducting type of the other layer become reverse to the above described type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which operates at a high speed by suppressing a short channel effect, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an ME formed on a GaAs substrate or the like has been known.
The SFET (MEtal Semiconductor FET) has an LDD structure (Lightly Doped Drai) to suppress the short channel effect.
n Structure), and a buried p-layer was provided under the LDD structure. Such a conventional example will be described in detail with reference to the drawings.

FIG. 8 is a sectional view of a conventional semiconductor device having a buried p-layer. In the figure, a semiconductor substrate 1 made of GaAs or the like has a gate electrode 8, a gate metal 9 on the gate electrode 8, a source electrode 1
0, a drain electrode 11 is formed. Then, a plurality of impurity layers of the same conductivity type are formed in the semiconductor substrate 1 immediately below these electrodes, thereby forming an LDD structure.

That is, an n-type active layer 3 serving as a channel region is formed under the gate electrode 8, and an n-type active layer 3 serving as a first source region is provided in the semiconductor substrate 1 between the gate electrode 8 and the source electrode 10. A layer 5 is formed, and an n ⁺ layer 4 as a second source region is formed below the source electrode 10.

Similarly, the gate electrode 8 and the drain electrode 11
An n ′ layer 6 serving as a first drain region is formed in the semiconductor substrate 1 between the semiconductor device 1 and an n ⁺ layer 7 serving as a second drain region is formed below the drain electrode 11.

Further, these n-type active layer 3, n 'layer 5,
6, one buried p layer 2 is formed below the n ⁺ layers 4 and 7 so as to cover these layers.
This constitutes an SFET.

[0007] In addition to an ME having a single buried p-layer as described above, an ME having a plurality of buried p-layers may be used.
There has also been an SFET in the past. FIG. 9 is a sectional view showing another conventional example having a buried p-layer. As shown in the figure, one buried p layer 2j is formed below the n-type active layer 3 and the n 'layers 5 and 6, and a new buried p layer 2i is formed below the n ⁺ layers 4 and 7. And 2k are formed. In this case, there are two types and three buried p layers.

[0008]

However, the above prior arts have the following disadvantages. For example, in the case where one type of buried p layer 2 shown in FIG. 8 is provided, if the difference between the thickness of the n-type active layer 3 and the thickness of the n ⁺ layers 4 and 7 becomes large, these three types of buried p layer are In order to cover the lower part of the n-type impurity layer, it is necessary to increase the impurity concentration in the buried p-layer. As a result, there is a problem that the neutral region that is not depleted increases and the capacity increases.

FIG. 10 is a cross-sectional view schematically showing the capacitance generated in the buried p-layer in FIG. As shown in the figure, a pn junction is formed between each of the n-type active layers 3, n 'layers 5, 6, and n ⁺ layers 4, 7 and the buried p layer 2, and a depletion layer 22 is generated. .

However, if the impurity concentration in the buried p-layer 2 is high, the neutral p-type layer 32 remains immediately below the gate electrode,
This produces an n-junction capacitance. Then, since the pn junction capacitance is charged and discharged at the time of switching of the semiconductor element, in such a conventional example, it has been difficult to realize a high-speed operation by slowing down the switching operation. On the other hand, if the impurity concentration in the buried p-layer is reduced so that a neutral p-type layer is not generated, there is a problem that the short channel effect is not sufficiently suppressed.

Therefore, in order to solve the problem of FIG. 8, two types of buried p-layers are formed as shown in FIG. 9, and three types of five n-type impurity layers are wrapped from below. Has been proposed. However, in FIG.
As shown in FIG. 1, the neutral p-type layers 33, 3 in the buried p-layer
Depletion layers 23, 24, 2 between 4, 35 and the n-type impurity layer
5, there is a problem that the electrical connection of these neutral p-type layers becomes insufficient.

Therefore, in such a case, the potential is not sufficiently determined in the neutral p-type layer 34, and the neutral p-type layer 34 becomes electrically unstable. Further, in FIG. 8, since it is difficult to connect the buried p layers 2i, 2j, and 2k by ion implantation, the buried p layers 2i, 2j, and 2k are not electrically stable, and the capacitance and the short channel effect due to the potential fluctuation of the isolated buried p layer are suppressed. The effect was sometimes deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has reduced the short-channel effect caused when the gate length is shortened, and improved the high-speed performance by reducing the gate capacitance. It is an object to provide a semiconductor device and a method for manufacturing the same.

[0014]

In order to achieve the above object, a semiconductor device according to the present invention is provided in a semiconductor substrate below the above-mentioned channel region, in contact with the above-mentioned channel region and a second conductive film. A first impurity layer of a second conductivity type is formed along a boundary of the first source region and overlapping a part of the first impurity layer. A third impurity layer of the second conductivity type is formed along the boundary of the first drain region and overlapping a part of the first impurity layer.
With such a configuration, the semiconductor device according to the present invention can achieve high-speed operation while suppressing the short-channel effect.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a first resist mask having a desired pattern on a semiconductor substrate and a step of forming a first resist mask on the main surface of the semiconductor substrate exposed from the first resist mask are performed. Forming a channel region by ion-implanting an impurity of a first conductivity type; and ion-implanting an impurity of a second conductivity type using the first resist mask as a mask to form the channel under the channel region. Forming a first impurity layer in contact with the region, removing the first resist mask, and forming a gate electrode by Schottky junction with the channel region; Forming a side wall on the side surface; and forming the second side around the gate electrode.
Forming a second resist mask for forming a source region and a second drain region, and using the gate electrode, the sidewall, and the second resist mask as a mask to form a first conductive type impurity. Ion-implanting to form the second source region and the second drain region, and removing the side wall, and then using the gate electrode and the second resist mask as a mask to form a first Ion-implanting a conductive impurity to form a first source region and a first drain region to a position shallower than the second source region and the second drain region; Using the second resist mask as a mask, ions of a second conductivity type are ion-implanted to form a second impurity layer below the first source region and to form an upper layer. The below the first drain region 3
Forming an impurity layer, performing a heat treatment after removing the second resist mask, and forming an ohmic contact with the source electrode and the drain electrode in the second source region and the second drain region, respectively. Joining. Therefore, the method for manufacturing a semiconductor device according to the present invention can manufacture a semiconductor device capable of suppressing a short-channel effect and realizing high-speed operation.

[0016]

Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing one embodiment of the present invention. 8, the same reference numerals as those in FIG. 8 denote the same or equivalent elements, and the point that is significantly different from FIG. 8 is that the buried p-layer 2a is provided below the n-type active layer 3 and the n ′ layers 5, 6. , 2b, and 2c.

That is, under the n-type active layer 3, a buried p-layer 2b is formed in contact with the n-type active layer 3, and the buried p-layer 2b extends from the side surface to the lower part of the n 'layers 5 and 6, respectively.
Layers 2a and 2c are formed.

As described above, since the buried p layers are individually provided in the n 'layers 5, 6 and the n-type active layer 3, the buried p layer 2b immediately below the gate electrode is thinner than that of FIG. Therefore, the size of the neutral region generated directly below the gate electrode can be extremely reduced,
The situation is as shown in FIG.

FIG. 3 is a cross-sectional view showing a depletion layer 20 and a neutral p-type layer 30 generated in the buried p-layer shown in FIG.
As shown in the figure, it can be seen that the thickness of the neutral p-type layer is smaller than that of the conventional example.

In FIG. 1, the width of the gate electrode 8 is shorter than the width of the n-type active layer 3 in order to shorten the gate length. You can make it longer.

In the following description, the case where the active layer below the gate electrode 8 is n-type will be described. However, when the active layer is p-type, the conductivity types of the respective layers may be reversed. If so, the technology according to the present invention can be applied as it is.

Next, another embodiment of the present invention will be described. FIG. 2 is a cross-sectional view showing another embodiment of the present invention. 1, the same reference numerals as those in FIG. 1 denote the same components, and buried p-layers 2e, 2f, and 2b under the n-type active layer 3 and the n 'layers 5, 6, respectively, as in FIG.
2g, and buried p layer 2 under n ⁺ layers 4 and 7
The feature of the present invention resides in that d and 2h are newly provided.

That is, below the n-type active layer 3,
A buried p layer 2f is formed in contact with type active layer 3, and n ′
Buried p-layers 2e and 2g are formed from the side surfaces to the lower portions of the layers 5 and 6, respectively. And furthermore, n ⁺
Since the buried p-layers 2d and 2h are formed in the layers 4 and 7 from the side surface to the lower part, leakage between the source and the drain can be surely prevented, and it can be said that this is more effective than FIG. .

Here, the manufacturing process of the semiconductor device shown in FIG. 2 will be described in detail with reference to the drawings. Figures 5, 6, and 7
FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device according to FIG. 2.
In step (a), a resist is applied to the semi-insulating semiconductor substrate 1 such as GaAs, and then a resist mask 40 having a desired pattern is formed. After that, the resist mask 4
An n-type active layer 3 is formed by implanting Si ions or the like as n-type impurities into the substrate surface exposed from zero.

In step (b), using the same resist mask 40 used when forming the n-type active layer 3,
Ions such as Be or Mg are implanted as p-type impurities. As a result, a buried p-layer 2f is formed below and in contact with the n-type active layer 3. The n-type active layer 3 and the buried p-layer 2f may be formed by epitaxial growth instead of ion implantation.

In step (c), after removing the resist mask 40, WSiN or the like is deposited over the entire main surface of the semiconductor substrate 1 by a sputtering method. Then, by using a resist mask (not shown) or an insulating film such as SiO ₂ as a processing mask, the shape of the deposited metal is processed, and the gate electrode 8 is formed on the n-type active layer 3 by Schottky junction.

In the step (d), the entire main surface of the semiconductor substrate 1 including the gate electrode 8 is removed by CVD using the CVD method.
An insulating film 41 such as iO ₂ is deposited. In step (e), the insulating film 41 is removed by anisotropic etching by the thickness of the insulating film 41, and the side wall 42 is formed on the side wall of the gate electrode 8.
To form

In step (f), a plurality of elements (not shown) formed on the semiconductor substrate 1 are covered with a resist, and thereafter a resist mask 43 having a desired pattern is formed. Si
Are ion-implanted. As a result, an n ⁺ layer 4 as a second source region and an n ⁺ layer 7 as a second drain region are formed on the semiconductor substrate 1.

In step (g), p-type impurities such as Be and Mg are ion-implanted using the same resist mask 43 used when forming the n ⁺ layers 4 and 7. As a result, a buried p layer 2d is formed under the n ⁺ layer 4,
A buried p layer 2h is formed below n ⁺ layer 7.

The depth at which the buried p layers 2d and 2h are formed is determined as follows. That is, if the implantation range is set to Rp at the time of ion implantation in the n-type impurity layer, the implantation energy of Rp + dRp is set slightly larger than Rp at the time of ion implantation to the buried p layer. As a result, a buried p-layer can be formed in contact with and under the n-type impurity layer.

Further, the implantation energy becomes more effective if it is determined as follows. That is, in consideration of the activation rate, the concentration and implantation energy are set such that the buried p-layer is completely depleted by the sum of the built-in diffusion potential and the drain voltage during operation on the drain side, and is built-in on the source side. The concentration and the implantation energy are such that the diffusion potential alone does not completely deplete.

As a result, the drain side buried p layer 2h
Is completely depleted by the drain voltage during operation and the internal potential due to the pn junction, and the electric field lines from the drain electrode are far away from the deep level of the substrate and the p-layer of the pn junction on the source side that has not yet been depleted. At the end.

The width of the depletion layer at this time is very large as shown in FIG. 4, so that the capacitance is small. Further, since the drain electrode is one of the electrodes, the equivalent circuit constant is Cgd. Or as Cds,
The FET as a whole has a low Cgd structure and a low Cds structure.

Next, in a step (h), the side wall 42 is removed by wet etching. In step (i), an n-type impurity such as Si is ion-implanted using the gate electrode 8 and the resist mask 43 as a mask, and the n ′ layer 5 as the first source region and the n ′ layer as the first drain region 6 are formed. 6 is formed.

In step (j), similarly, p-type impurities such as Be and Mg are ion-implanted using the gate electrode 8 and the resist mask 43 as a mask, and the buried p-layers 2e and 2g are implanted.
To form Here, it is more effective to control the implantation energy for forming these buried p layers 2e and 2g in the same manner as in step (g).

In step (k), after removing the resist mask 43, a protective film (not shown) is formed over the entire front and back surfaces of the semiconductor substrate 1, and then heat treatment is performed to activate the ion-implanted impurities. I do.

Thereafter, AuGe / Ni is deposited on the n ⁺ layer 4 and ohmic-joined to form a source electrode 10. Similarly, AuGe / Ni is ohmic-joined on the n ⁺ layer 7 to form a drain electrode. 11 is formed.

Thereafter, Au is formed on the gate electrode 8.
Is deposited to form a gate metal 9, a field-effect transistor according to the present invention is completed. In the completed semiconductor device according to FIG. 2, when a drain voltage is applied, a buried p-layer is formed as shown in FIG. , A depletion layer 21 and a neutral p-type layer 31 are formed.

In steps (g) and (j),
If the pattern is enlarged by performing resist shrink on the resist mask during ion implantation, the buried p-layer can be formed more reliably. Of course, even if the buried p-layer is formed in this way, the above effect is not impaired. Also, needless to say, if the buried p-layers 2d and 2h are not created in step (g), the semiconductor device according to FIG. 1 is created.

[0040]

As described above, according to the present invention, the buried layers are individually formed in the channel region, the first source and drain regions, and the second source and drain regions. As a result, a neutral region is not formed immediately below the gate, and the gate capacitance can be reduced. Therefore, a high-speed operation can be realized as compared with the conventional one. Further, by completely depleting the buried layer on the drain side with the built-in diffusion potential and the drain voltage, the potential is easily supplied from the source side to the buried layer immediately below the gate electrode. As a result, the buried layer immediately below the gate electrode is electrically coupled only to the source side and becomes electrically stable. Furthermore, since there is no coupling with the drain side,
Cgd, which greatly affects the speed performance, does not occur, which is effective in suppressing the short channel effect.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing another embodiment of the present invention.

FIG. 3 is a sectional view showing a capacitance generated in a buried p-layer in FIG.

FIG. 4 is a sectional view showing a capacitance generated in a buried p-layer in FIG. 2;

FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device according to FIG. 2;

FIG. 6 is a sectional view showing a manufacturing step of the semiconductor device according to FIG. 2;

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to FIG. 2;

FIG. 8 is a sectional view showing a conventional example.

FIG. 9 is a sectional view showing a conventional example.

FIG. 10 is a sectional view showing a capacitance generated in a buried p-layer in FIG.

11 is a cross-sectional view showing a capacitance generated in a buried p-layer in FIG.

[Description of Signs] 1 ... Semiconductor substrate, 2, 2a, 2b, 2c ... Embedded p
Layer, 3 ... n-type active layer, 4,7 ... n ⁺ layer, 5,6 ... n '
Layer: 8 gate electrode, 9 gate metal, 10 source electrode, 11 drain electrode.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kiyomitsu Onodera 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (6)

[Claims] A gate electrode, a source electrode, and a drain electrode are formed on a main surface of the semiconductor substrate; a channel region of a first conductivity type is formed in the semiconductor substrate below the gate electrode; And a first source region of a first conductivity type is formed in the semiconductor substrate between the source electrode and the gate electrode. The first source region is in contact with the first source region, and A second source region is formed in the lower semiconductor substrate to the same conductivity type as the first source region and deeper than the first source region. A first drain region of a first conductivity type is formed in the semiconductor substrate between the electrode and the gate electrode; A field effect transistor in which a second drain region of the same conductivity type as the first drain region and deeper than the first drain region is formed in the semiconductor substrate below the drain electrode; A first impurity layer of a second conductivity type is formed in the semiconductor substrate below the channel region in contact with the channel region, along a boundary of the first source region, and
And a part of the second conductive type second layer.
And a third impurity layer of the second conductivity type is formed along the boundary of the first drain region and overlapping a part of the first impurity layer. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein said second source region extends along a boundary thereof and said second source region extends along a boundary thereof.
And a part of the impurity layer of the second conductivity type.
And a fifth impurity layer of the second conductivity type is formed along the boundary of the second drain region and overlapping part of the third impurity layer. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein the third impurity layer is completely depleted by an operation voltage applied to the drain electrode. 4. The semiconductor device according to claim 2, wherein at least one of the third and fifth impurity layers is completely depleted by an operation voltage applied to the drain electrode. 5. A step of forming a first resist mask of a desired pattern on a semiconductor substrate, and ion-implanting a first conductivity type impurity into a main surface of the semiconductor substrate exposed from the first resist mask. Forming a channel region by performing ion implantation of impurities of a second conductivity type using the first resist mask as a mask, and forming a first impurity layer under the channel region so as to be in contact with the channel region. Forming a gate electrode by Schottky bonding to the channel region after removing the first resist mask; forming a sidewall on a side surface of the gate electrode; Forming a second resist mask for creating the second source region and the second drain region around a gate electrode; Forming a second source region and a second drain region by ion-implanting an impurity of a first conductivity type using the side wall and the second resist mask as a mask; After the removal, the impurity of the first conductivity type is ion-implanted using the gate electrode and the second resist mask as masks, and the impurity is ion-implanted to a position shallower than the second source region and the second drain region. Forming a first source region and a first drain region, and ion-implanting a second conductivity type impurity using the gate electrode and the second resist mask as a mask;
Forming a second impurity layer below the source region and forming a third impurity layer below the first drain region; and performing a heat treatment after removing the second resist mask. The second source region and the second drain region,
Forming a ohmic junction between the source electrode and the drain electrode. 6. The method according to claim 5, wherein after the step of forming the second source region and the second drain region, the step of forming the second source region and the second drain region is performed using the gate electrode, the sidewall, and the second resist mask as masks. Implanting an impurity of a second conductivity type, forming a fourth impurity layer below the second source region, and forming a fifth impurity layer below the second drain region. A method for manufacturing a semiconductor device, comprising: