JPS61149345U - - Google Patents

Info

Publication number
JPS61149345U
JPS61149345U JP3208585U JP3208585U JPS61149345U JP S61149345 U JPS61149345 U JP S61149345U JP 3208585 U JP3208585 U JP 3208585U JP 3208585 U JP3208585 U JP 3208585U JP S61149345 U JPS61149345 U JP S61149345U
Authority
JP
Japan
Prior art keywords
conductive terminal
semiconductor device
insulating base
package
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3208585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3208585U priority Critical patent/JPS61149345U/ja
Publication of JPS61149345U publication Critical patent/JPS61149345U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の上面図、第2図は
従来のパツケージの上面図、第3図は第2図にお
ける―断面図、第4図は第1図における―
断面図である。 1……絶縁基体、2,3,4……導電端子、5
……半導体装置、7……凹部。
Fig. 1 is a top view of an embodiment of the present invention, Fig. 2 is a top view of a conventional package, Fig. 3 is a sectional view of Fig. 2, and Fig. 4 is a sectional view of Fig. 1.
FIG. 1... Insulating base, 2, 3, 4... Conductive terminal, 5
...Semiconductor device, 7...Recess.

Claims (1)

【実用新案登録請求の範囲】 (1) 絶縁基体と、この絶縁基体の上に固着され
た第1の導電端子と、この第1の導電端子とは離
間して前記絶縁基体の上に固着された第2の導電
端子とを含み、前記第1の導電端子の上に半導体
装置が固着される半導体装置のパツケージにおい
て、 前記第1の導電端子と前記第2の導電端子とが
対向する部分の前記絶縁基体材料が、削除されて
いることを特徴とする半導体装置のパツケージ。 (2) 前記第1の導電端子および前記第2の導電
端子のうち、少なくともどちらか一方の導電端子
の端部は、他方の導電端子に近づくにつれて、端
子幅が小さくなるように形成されていることを特
徴とする実用新案登録請求の範囲第1項記載の半
導体装置のパツケージ。
[Claims for Utility Model Registration] (1) An insulating base, a first conductive terminal fixed on the insulating base, and a first conductive terminal fixed on the insulating base at a distance from each other. A package of a semiconductor device including a second conductive terminal and a semiconductor device fixed onto the first conductive terminal, wherein the first conductive terminal and the second conductive terminal face each other. A package for a semiconductor device, wherein the insulating base material is removed. (2) An end of at least one of the first conductive terminal and the second conductive terminal is formed such that the width of the terminal becomes smaller as it approaches the other conductive terminal. A semiconductor device package according to claim 1, characterized in that:
JP3208585U 1985-03-06 1985-03-06 Pending JPS61149345U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3208585U JPS61149345U (en) 1985-03-06 1985-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3208585U JPS61149345U (en) 1985-03-06 1985-03-06

Publications (1)

Publication Number Publication Date
JPS61149345U true JPS61149345U (en) 1986-09-16

Family

ID=30533272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3208585U Pending JPS61149345U (en) 1985-03-06 1985-03-06

Country Status (1)

Country Link
JP (1) JPS61149345U (en)

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