JPS61148545A - Memory control device - Google Patents

Abstract

PURPOSE:To control under optimum condition data transfer to a memory with simple constitution, by converting the bit length of data in accordance with the identified result of a memory access request. CONSTITUTION:For instance, in case when a write request of 8 bits has been generated by a memory write request from an encoder 202, it is bundled to 16-bit length by a bit length converting circuit 205 and stored in a VRAM 204. A transmitting I/F circuit 206sends out an image information code which has been read out of the VRAM 204 onto a circuit. On the other hand, the VRAM 204 is a large-capacity memory, and sometimes is used as a storage memory of data from a CPU 207, for instance, communication management information and self-diagnostic information. In this case, write or readout is requested by a CPU memory write request or a CPU readout request. As for these requests, the bit length converting circuit 205 does not execute bit length conversion.

Description

[Detailed description of the invention] [Technical field" The present invention relates to a memory control device.

E. Prior Art In a device in which CPUs and peripheral processing circuits of different bit lengths coexist, it is troublesome to configure a system by connecting them with a bus. This is particularly the case when a large capacity memory such as a video memory (hereinafter abbreviated as VRAM) is connected to such a system and memory access/data transfer is performed. In the US, each circuit was equipped with an interface (hereinafter abbreviated as I/F) circuit for changing the length to match the processing bit length of the rotor.

For example, in the case of a facsimile machine with the configuration shown in Figure 1, if the cputoi is 16 bits, the VRA
MI02 is normally set to 16 bits. Then, the circuits that perform 8-bit processing, namely the encoder 103, decoder 104, transmission 1/F circuit 105, receive! /F circuit 106 cannot be directly connected to the pass line, so 8-bit → 16-bit conversion circuits 107 and 11
0, and 16-bit → 8-bit conversion circuits 108, 109
Via! It will be connected to the S-sline. However, providing each component with the conversion circuit described above has many disadvantages, such as complicating the cost and configuration of the entire device.

The present invention was made in view of the above-mentioned drawbacks, and its purpose is to provide ff!
An object of the present invention is to provide a memory control device that optimally controls data transfer to and from a memory using an iqi configuration.

L Embodiment" FIG. 2 shows the one-prong side of the present invention, taking a facsimile machine as an example.

A document reader 201 reads a transmitted document and converts it into an electrical signal. An encoder 202 compresses the redundancy of the image information of the transmitted document and converts it into an 8-digit code. 203 is a request processing circuit, which determines the priority order of memory access requests from each component, 204 is an image RAM (hereinafter referred to as VRAM), which stores data in units of 16 bits; and 205, which performs bit length conversion. For example, if an 8-bit write request is generated from the encoder 202 by a memory write request (hereinafter abbreviated as ENCWR), the bit length conversion circuit converts the bit length depending on the source of the memory access request. 205 is bundled into 16-bit length and stored in VRAM 204, 206 (transmission 1/Fll path, VRAM
The image information code read from 204 is sent out on the line, and at this time also a transmission memory read request (hereinafter TRNR) is sent.
(abbreviated as D), when an 8-bit read request is generated, the bit length conversion circuit 2054t
6 bits l) information NI8 bits) decomposes into 18 pieces and sends them out on the pass line 0 or more are operations leading to transmission.

The VRAM 204 is a large-capacity memory, and may be used temporarily as a memory for storing data from the CPU 207, such as communication management information and self-diagnosis information. At this time, writing or reading is requested by a CPU memory write request (hereinafter abbreviated as cpuwR) or a CPU read request (hereinafter abbreviated as CPURD). For these requests, the p&- conversion circuit 205 does not perform bit length conversion.

When receiving, receive the signal from the line @17F circuit 21
0 is received and written to 204. At this time, the bit length conversion circuit 205 performs 8-bit → 16-bit conversion according to the received write request signal (hereinafter abbreviated as R1CWR), and 211 is the image information stored in the VRAM 204. This is a decoder for decoding a code into an image signal.

The bit length conversion circuit 205 converts from 16 bits to 8 bits in response to the read request signal DECHD from the decoder 211. 212 is a recording printer;
Record the image signal decoded by and output it on paper0
The above is the reception operation.

FIG. 3 shows an example of the configuration of the bit length conversion circuit 205. The principle of the bit length conversion circuit 205 is as shown in the operation explanation in FIG. The access request signal is decomposed into 8 bits depending on the request source of the access request signal. Furthermore, bit length conversion may not be performed.

In Figure 3, the pass line has a 16-bit configuration, but
Inside the bit length conversion circuit, the upper 8 bits (hereinafter referred to as BUS
The LSB (abbreviated as LSB) and the lower 8 bits (hereinafter abbreviated as BUSMSB) are handled separately. Furthermore, input/output devices with an 8-bit length (encoders, decoders, etc. in Figure 2) are the lower 8 bits.
Only bits shall be used.

The operation of the circuit shown in FIG. 3 will be explained.

(Cpu read/write requests) In normal cases, for example, when there is a 16-bit write or read request from the CPU, cpuwR or
PURD (7) ff The desired signal passes through the OR gate 301 or 302 to access the memory. In such cases, bit length conversion is not performed.

(In the case of 8-bit → 16-bit conversion) When a write request is made from an 8-bit processing circuit such as an encoder, EMCIIR is generated. This is a flip-flip (hereinafter abbreviated as FF) via a NOR gate 303.
304 is driven. Since the FF 304 constitutes a frequency divider circuit, the output of the NOR gate 305 is generated once every two times. Ten thousand.

306 is a D type 8-bit latch, ENCW
BUSLSB is latched every two times when R is input. Further, 307 is a path driver that loads the latch data written one place before the latch 306 by the output of Q/II of the F/F 304 onto the upper 8 bits of the memory path of the VRAM 204.

The upper 8 bits of the memory path of VRAM204 are VR below.
AMMSB, 下ffl 8 hi', / ト e VR
ANLSB,! :Omitted.

In this way, 8 bits are bundled into 16 bits and input to the VRAM 204 once every two times. At this time gate 305
Since the output of 1 drives the VRAM to write through the gate 301, 16-bit data is written to the VRAM after all. This operation is similar to the access request RECWR from the reception 1/F circuit 210.The conversion operation from 8 bits to 16 bits is explained below.Next, referring to FIG. 4, when writing to memory Explain the timing. Figure 4 shows that when the write request ENCWR is sent from the encoder 202 twice in a row, the first code (7) ENCWRf BUSLSB is "A", but the second ENCWR is -B" for BUSLSB. This is a timing chart from when a code is sent from the encoder 202 until it is converted into 16-bit 'A B'.

To explain in order, first, the FF 304 is set at the first falling edge of ENCWH. The Q side output of FF304 and the output of gate 303 are input to gate 312, and gate 31
At the rising edge of the second output, the contents of auscsa are latched into the latch 306. At this time, BUSLSH has the first E
Since the code °A'° is carried in synchronization with NCWH, the content of the latch 306 becomes "A", and the gate 31
2 output is F/F 304 at the second ENCWH
is set, so it does not become "l", therefore,
At the second -ENG1ilR, the contents of the latch 306 are not changed.

When the second ENCWR comes, FF304 is set and WR is sent to Ilnotecate 305, 301 and VRAM204. VRAM 204 prepares for a write operation. Predetermined address information is carried on an address bus (not shown) for each memory access, but since WR is not output during the first ENCWH, the address is not latched in the VRAM 204, but is latched by the second ENCWH.

2@th+7) ENCWR card, VRAM204
The FF 304 is reset while sending the WR. F
When F304 is reset, the bus driver 307 is enabled by the Q/bias of FF304, and the latch 306
The content "'A'" is output to VRAMN5B. Now VRAMMSB Niha”A”! 1-)”K, VRA
IIILSH d has the code 'B' on it,
Eventually, 16 bits are written all at once to the VRAM 204 for which writing preparations have been completed.

(In the case of 18-bit → 8-bit conversion) Next, we will explain the case of a read request from an 8-bit processing circuit.
Set 09. FF309 is a divide-by-2 circuit like FF304, and drives gate 311 or 310 once every two times, but never at the same time.The output of gate 311 reads VRAM via OR gate 302. This becomes the driving RD. RD according to the first TRNRD causes the VRAM204 to be used for the second time (7)T.
RNRD (7) The 16-bit data is VRAMN before
5B, VRAMLSB IC output. Therefore, during the second TRNRD, VRAMN5 was sent via Game) 310.
The 8 bits of H are latched into a latch 312, and the contents of the latch 312 are placed on BUSLSH as described later. In this way, the transmission 1/F circuit 206 takes in data 8 bits at a time.

FIG. 5 is a timing chart for converting from 16 bits to 8 bits. First, since FF309 is reset at the first rise of TRNRD, gate 3
The RD is sent to the VRAM 204 through 11,312. 8
VRAM 204 takes over and begins a read cycle. Also, FF309 is set at the falling edge of TRNRD. 2nd +7) VRAM before TRNRD comes
Assume that MSB, VRANLSB *8-bit data, for example, "A" and "B" are read out. FF3
Since 09 is set.

Bus driver 313 is not enabled.

Follow, BUSLSB NiltVRAMLSB (7
) The data "B" is carried as is, therefore, the transmission 1/F circuit 206 BUSLSB (7) "B" is removed.

When the second TRNRD is sent from the transmitting I/F circuit 206, the L? V
Although not shown in FIG. 5, the readout output of the VRAM 204 is set to an open state immediately after being fetched into the latch 312. Therefore, the second T
When the FF 309 is reset at the falling edge of RNRD, the bus driver 313 is enabled, so the latch 31
Data A' latched at 2 is placed on BUSLSB. The transmission 1/F circuit receives this second data "'B"
is fetched from BUSLSB.

In this way, the 16-bit data read from the VRAM 204 is divided into two pieces of 8-bit data and sent in sequence to the device that sent the read request.

As explained above, when the processing data length of the device that requested memory access is 8 bits, when the memory access is for reading data, the data read from the memory is 1 bit.
6-bit data is converted into two 8-bit data,
Conversely, when writing, two 8-bit data are converted into 16-bit data and written into the memory.

Although the above embodiment is an example of bit length conversion between 8 bits and 16 bits, it can be easily applied to other bit lengths, for example, when the memory bit length is 32 bits, and the conversion type can also be changed. It is also possible to increase the number.

E effect" As explained above, according to the present invention, even if a plurality of devices that access memory with a bit length different from the memory bit length are connected to a common bus, optimal bus coupling can be provided. This makes it possible to reduce the cost of the entire device due to its simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example, Fig. 2 is a block diagram of an embodiment applied to a facsimile, Fig. 3 is a circuit diagram of the embodiment, Fig. 4 is a timing chart for writing in the embodiment, and Fig. 5 is a timing chart at the time of reading in the embodiment. In the figure, 202...encoder, 203...request processing circuit, 204...VRAM, 205...bit length conversion circuit 206...transmission 1/F circuit.

Claims (1)

[Claims] In a memory control device that controls reading/writing of data in the memory between a memory that stores data and a plurality of memory access request units that access the memory, a memory access request from the memory access request unit is identified. 1. A memory control device comprising: an identifying means for determining the data; and a bit length converting means for converting the bit length of the data according to the identification result of the identifying means.