KR940006833B1 - Apparatus for controlling the request on common resources - Google Patents

Abstract

The apparatus improves the performance of the overall system so that the desired data can be accessed no matter what the system bus size is. The system comprises; a shared resource memory unit (22); an address buffer storing the specified area address of the shared resource; a control and decoder unit (24) controlling a bidirectional buffer (21) and the shared memory unit (22) in order to transmit the stored data of the memory unit into the bidirectional buffer; a buffer (23) summing the address from the decoder (24) and the address from an address buffer (25).

Description

Shared resource access request control device

1 is a block diagram of a multi-processing system to which the present invention is applied.

2 is a diagram for explaining a conventional shared resource access method by a system controller to which the present invention is applied.

3 is a view for explaining a shared resource access method according to the present invention.

4 is a detailed circuit diagram of the control & decode means of the present invention.

* Explanation of symbols for main parts of the drawings

1 System Controller Board 2 CPU Board

3: main memory board 4: input / output processing board

5: System Bus 11,20: Bus Data Buffer

10,25 Address buffer 21 Bidirectional buffer

13,22: shared resource storage 29: PAL (Programmable Array Logic)

32,33: counter 36,37: decoder

The present invention is an apparatus for accessing a shared resource in a system control module (SCM) having a size of 1 byte in a multiprocessing system based on a system bus. It is about.

In the conventional multiprocessing system having a shared resource, as shown in FIG. 1, several central processing units (P * 1 to P # n) (2) and input / output equipment (IOP # 1 to IOP) based on the system bus are shown. It consists of boards such as #n (4) and main memory boards (M # 1 to M # n) (1), and must be shared and accessed by central processing unit 2 and I / O processing unit 4, etc. The printer interface, the console, the real time clock (RTC), the configuration memory (Configuration Memory), which are resources that cannot be placed in the main memory, are shared and accessed in the system controller 1.

This shared resource has a data size of mode 1 byte.

In contrast, the system bus 5 has a data size of 8 bytes.

Therefore, in the system having such a structure, the central processing unit 2 or the input / output unit 4 may require 1,2,4,8 bytes of the size to access when accessing the shared resource on the system bus 5.

2 is a block diagram illustrating a shared resource access method of a conventional system controller.

The board which wants to access the shared resources in the system controller (1 in FIG. 1) on the system bus 5 is given a bus right through arbitration for bus use.

When the bus license is obtained through this arbitration process, the board that wants to access the shared resources will have the address, transfer type (TT), byte enable (BE) and address space (AS) in the address transfer period. ) Signal is transmitted to the address buffer 10 so that the address buffer 10 latches these signals.

The decoder 15 decodes specific signals among the signals latched in the address buffer 10 to determine whether a request of a board currently wishing to access is a read or write operation 14. ) Is provided to the shared resource storage unit 13.

In addition, the decoder 15 provides the buffer enable signals BEC0 to BEC7 for enabling only one of the eight data buffers 12 to the data buffer 12.

In the case of a write operation on the shared resource, the bus data buffer 11 latches data from the system bus 5 and buffers the buffered data through the buffer data bus 9. ) As it is.

At this time, only the buffer enabled by the decoder 15 is operated so that one byte of data is provided to the shared resource storage unit 13. In the case of the read operation, data generated in the shared resource storage unit 13 by the control signal of the decoder 15 and the local address signals LA0 to LA31 transmitted through the local address bus 17 are stored in eight data buffers ( 12) The data is transferred only to the enabled buffer, and the data thus transferred is transferred to the bus data buffer 11 through the buffer data bus 9, and the transferred data is transferred to the system bus 5, thereby providing 1 byte of data. The read operation is completed.

In a system having such a structure, a processor inside the board requiring data access must access a shared resource with a size of 1 byte only. When accessing 2, 4, or 8 bytes, 2, 4, 8 times are required. It must be accessed repeatedly using the system bus 5.

Therefore, the conventional system has a problem in that the performance of the system bus 5 is degraded due to such repeated access.

It is an object of the present invention to access as many data (up to 8 bytes) as desired using only one system bus regardless of the access size (1, 2, 4, 8 bytes) required by a board connected to the system bus. To improve the performance of the overall system.

In order to achieve the above object, the present invention provides a shared resource storage unit for storing a shared resource, an address buffer which is transmitted through a system bus and stores an address of a specific area of the shared resource storage unit, and is input and output to the system bus. A shared resource access request control device including a bus data buffer for temporarily storing data and a bidirectional buffer for temporarily storing data input / output to the shared resource storage unit, wherein the access stored in the address buffer is used as an initial access address. The access to the shared resource storage unit is repeated as many times as the number of bytes requested, but when the write transfer operation is performed, the data stored in the bidirectional buffer is sequentially transmitted to the shared resource storage unit, and the read transfer operation is performed. When performing the shared resource Control and decoding means for controlling the bidirectional buffer and the shared resource storage unit so that data stored in the unit is sequentially transferred to the bidirectional buffer, and an address output from the address buffer and an output from the control & decode means. Contains a buffer that sums addresses.

In addition, the control & decode means is a PAL (Programmable Array Logic) performing the decoding function, the encoding function and the state control function, and the access byte number signal (icd <2..0>) provided from the PAL as an initial value. A down counter for accepting and decreasing the coefficient, and the shared resource storage unit to receive the address signal scd <3..0> provided from the PAL as an initial value and increase the coefficient to sequentially access An up counter for determining an address and an access completion signal (acc end) for notifying an access completion to a higher module in synchronization with a counter completion signal (end) outputted after the down counter completes counting. It is enabled by a flip flop and the control signals DE * and R / W provided from the PAL, and the output signal ca <3 .. Decipher 0>) The first decoder provides a read control signal (rpc <7.0>) to the bidirectional buffer and the control signals DE * and R / W provided from the PAL enable the write access operation. To this end, it comprises a second decoder which decodes the output signal ca <3..0> of the up counter and provides a write control signal rpc <7..0> to the bidirectional buffer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a shared resource access method according to the present invention.

When a specific board on the system bus 19 receives an access request for the shared resource storage unit 22 in the system controller, the specific board outputs an address of a specific area of the shared resource storage unit 22 to be accessed. The address is stored in the address buffer 25.

In this way, using the address stored in the address buffer 25, the control & decode circuit 24 decodes the size of the byte to be accessed, the address, and the like to determine the shared resource to be accessed and the address to be accessed. Give it.

The control & decode circuit 24 repeats the access to the shared resource storage 22 as many times as the number of bytes requesting access using the address stored in the address buffer 25 as an initial address. When performing the transfer (wirte transfer) transfers the data of the bus stored in the bi-directional buffer 21 to the shared resource storage unit 22 and transfers the data of the shared resource storage unit 22 via the read transfer (read transfer) Read and latch to bidirectional buffer 21.

The bus data buffer 20 stores or transmits 8 bytes of system data.

Therefore, in the case of a write operation, the bus data buffer 20 latches data (up to 8 bytes) on the bus and simultaneously transfers the latched data to both buffers 21.

At this time, the bidirectional buffer 21 receives the control signal of the control & decode circuit 24, and the bidirectional buffer 21 corresponding to the number of bytes (1, 2, 4, 8 bytes) that has been written request is enabled in turn so that each buffer 1 byte of data is sequentially transferred to a given address area of the shared resource 22.

In the case of a read operation, the bidirectional buffer 21 receives the control signal of the control & decode circuit 24 and sequentially stores data stored in a given address area of the shared resource storage unit 22 in the corresponding bidirectional buffer 21. After the data is repeatedly transmitted and stored by 1 byte, the data is transferred to the bus data buffer 20 when the number of data in the bidirectional buffer 21 is equal to the number of data requested for access.

The bus data buffer 20 then transfers this data to the system bus 19 to complete the read operation.

Therefore, when the conventional method shown in FIG. 2 intends to access the shared resource 13 in the system controller 1 by more than 1 byte in size, the access must be retried using the system bus 19 as many as desired. In the method of the present invention shown in FIG. 3, data can be accessed as many times as desired (up to 8 bytes) using only one system bus.

The control & decode circuit 24, which is the most important circuit for operating this structure, is shown in FIG. Important components of the control and decode circuit 24 include a programmable array logic (PAL) 29 and a down counter (PAL) that perform decoding and encoding functions and state control functions. 32, an up counter 33, a flip flop 34, decoders 36, 37, and so forth.

The PAL 29 encodes a signal be <7..0> received from an address buffer (25 in FIG. 3) which latches an address related signal transmitted from a system bus and accesses the down counter 32. The initial value (icd <2..0>) indicating the number is provided, and the initial address (ba <3..0>) of the shared resource to be accessed is encoded to the Up Counter 33. Provided as the initial value (scd <3..0>).

The flip flop 34 synchronizes with an access end signal generated when the value of the down counter 32 becomes "0", that is, when access is completed by a desired number of bytes. By providing the control module as the upper module, the control circuit can perform the following operations.

The up counter 33 increases the count starting from the initial address value scd <3..0> received from the PAL 29, thereby increasing the count (ca <3..0). &Quot;) and the decoder decodes the 3-bit address into an 8-bit address (3 TO 8) to control the operation of the corresponding buffer among the 8 bidirectional buffers (21 in FIG. 3).

The PAL 29 provides the icd <2..0> and scd <3..0> signals to the down counter 32 and the up counter 33 as initial values, respectively, where the icd signal is a count number (ie access). The hexadecimal value equal to the requested number of bytes) should be generated, and the scd signal is increased by subtracting 1 from the value of the signal ba <3..0>, which is stored in the address buffer (25 in Figure 3). The initial value of the counter 33 should be loaded because the address value increased by 1 from the initial value of the up counter 30 becomes the access address of the last shared resource.

The decoder of the present invention includes a decoder 36 for generating a rpc <7..0> signal, which is a signal for controlling the bidirectional buffer (21 in FIG. 3) in an access for a read operation, and a control of the bidirectional buffer during a write operation. There is a decoder 37 for generating a wpc <7..0> signal which is a signal responsible for.

When access to shared resources is required for a write operation, data is stored by sequentially enabling the corresponding buffers in the bidirectional buffer (21 in FIG. 3) that latches data transmitted from the bus data buffer (20 in FIG. 3). Although it may be provided to the shared resource storage unit 22 sequentially, when an access is required for a read operation, the shared resource storage unit 22 receives the request from the read access before transmitting data from the shared resource storage unit 22 to the bus data buffer 20. The data is read in the bidirectional buffer 21 until the number of bytes is reached.

At the time of completion of storing, the data stored in the bidirectional buffer 21 by the number of bytes requested for access are transferred to the bus data buffer 20 at one time.

PAL 29 provides two signals DE *, R / W to decoders 36 and 37.

The decoders 36 and 37 are enabled only when the two signals input to the two terminals E1 and E2 simultaneously have a low value.

The DE * signal generated by the PAL 29 is input to two decoders 36 and 37 in common, and this signal DE * is a btt <3..0> signal provided from the address buffer 25. PAL29) is the signal decoded.

The PAL 29 also outputs an R / W signal for determining the read operation and the write operation.

This signal R / W is used to determine the decoder to enable.

That is, if the R / W value is low, the write operation is performed, and if the R / W value is high, the read operation is performed.

Accordingly, if the R / W signal is low, decoder # 2 37 is enabled and decoder # 1 36 is disabled.

On the other hand, if the R / W signal is high, the value becomes Low through the inverter 35 and the decoder # 1 36 is enabled, and the decoder # 2 has a high signal. Since it is input as it is, decoder # 2 37 becomes disabled and does not operate.

As described above, according to the present invention, any board connected to the system bus can access the shared resources stored in the system controller only once, regardless of the access size (1, 2, 4, 8 bytes) required by the board. It can also be used to access as many shared resource data as desired.

Claims (2)

A shared resource storage 22 storing a shared resource, an address buffer 25 which is transmitted through a system bus 19 and stores an address of a specific area of the shared resource storage 22, and the system bus ( 19. A shared resource access request control apparatus including a bus data buffer 20 for temporarily storing data input / output to 19) and a bidirectional buffer 21 for temporarily storing data input / output to the shared resource storage 22. When the address stored in the address buffer 25 is an initial access address, the access to the shared resource storage unit 22 is repeated as many times as the number of bytes requesting access, but the write transfer operation is performed. When the data stored in the bidirectional buffer 21 are sequentially transmitted to the shared resource storage unit 22 and the read transfer operation is performed, the shared resource storage unit 22 is transmitted to the shared resource storage unit 22. Control and decoding means 24 for controlling the bidirectional buffer 21 and the shared resource storage 22 to sequentially transmit the stored data to the bidirectional buffer 21, and to the address buffer 25. And a buffer (23) for adding up the address outputted from the address and the address outputted from the control & decode means (24). 2. The control and decode means (24) according to claim 1, characterized in that the control & decode means (24) comprises a PAL (29) for performing decoding means, an encoding function and a state control function, and an access byte number signal (icd &lt; 2) provided from the PAL (29). .0>) as an initial value, and the down counter 32 for decreasing the coefficient and the address signal scd <3..0> provided from the PAL 29 are taken as an initial value to increase the coefficient. An up counter 33 for determining an address of the shared resource storage 22 to be sequentially accessed, and a counter completion signal (end) output by the down counter 32 after completing the counting, to a higher module. It is enabled by the flip-flop 34 which outputs an access completion signal (acc end) for notifying the completion of the access, and the control signals DE * and R / W provided from the PAL 29 and read access. For operation, the output signal ca <3..0> of the up counter 33 is decoded. A first decoder 36 for providing a read control signal (rpc <7 .. 0>) to the bidirectional buffer 21 and the control signals DE *, R / W provided from the PAL 29; ) Is enabled and the output signal ca <3..0> of the up-counter 33 is decoded for the write access operation, and the write control signal wpc <7. And a second decoder (37) for providing &lt; 0 &gt;).