KR930005709B1 - Rack addressline multi-function operating system of plc - Google Patents

Abstract

The duplex rack address line communicates data between a programmable logic controller and special I/O cards having CPU and common RAM. The system includes a chip selection signal generator (10) for combining address signals (A13-A15) of a CPU to generate chip selection signal, a slot connector for interfacing chip selection signal, a read/write signal generator (17) for combining read/write signal, chip selection signal (CS0), byte signal (BY2) and data signal to generate read/write control signal, an I/O processing CPU (19) for controlling an I/O cards according to interrupt signal (INT) and fine (FIN) signal generated by the read/write signal generator (17), a common RAM (21) for storing I/ O data of the CPU (19), a transmitter/receiver (18) for transmitting output data of the CPU (19), a transmitter/receiver (18) for transmitting output data of the CPU (19) to the slot connector (11), and a multiplexer (20) for storing address signals (A0-A13), and read/write signal on the common RAM (21).

Description

PLC's rack address line multi-function system

1 is a schematic configuration diagram of a rack of a conventional PLC.

2 is a diagram of a conventional main CPU cart in which the connector of FIG. 1 is interpolated.

3 is a block diagram of a conventional input / output card inserted into the connector of FIG.

4 is a schematic configuration diagram of a rack of the present invention PLC.

5 is a block diagram of the main CPU card of the present invention inserted into the connector of FIG.

Figure 6 is a block diagram of a special input and output card of the present invention interpolated to the connector of Figure 4.

* Explanation of symbols for main parts of the drawings

1: Main Rack 2: Expansion Rack

3: Main CPU 4: Program ROM

5: RAM 10: Chip select signal generator

11 slot connector 17 read / write signal generator

18: transceiver 19: input and output central processing unit

The present invention relates to the use of a limited address line installed in a rack in a programmable logic controller (PLC). In particular, a CPU and a common RAM are embedded in a special input / output card (I / O card) to be inserted into a rack. The present invention relates to a rack address line plural function implementation method of a PLC for enabling a smooth exchange of information when there is.

As shown in FIG. 1, the rack of the conventional PLC is divided into a main rack 1 and an expansion rack 2, and the main rack 1 includes a plurality of 14 address lines A0-A13. The connectors 1a-1j are sequentially connected, and the decoder 1k is connected to the connector 1b to decode the data output from the connector 1b to select the respective on connectors 1c-1j. It will be enabled.

In addition, a plurality of connectors (2a-2j) of 14 dress lines (A0-A13) are sequentially connected to the expansion rack (2), and the connectors (2b) enable the plurality of connectors (2c-2j). The decoder section 2k is connected and a multiplexer 21 for selecting the decoder section 2k is connected, and the connector 2b of the expansion rack 2 is connected to the connector of the main rack 1. It is connected with 1a).

2 is a configuration diagram of the main CPU card. The slot connector 9 is connected to the connector 1b of the main rack 1 to interface data, and the buffer unit buffers data of the slot connector 9. (8), a decoder unit 7 for decoding the output data of the buffer unit 8, a buffer unit 6 for buffering the output data of the slot-connected connector 9, and the buffer unit 6 And the output data of the decoder unit 7 are stored in the RAM 5 in accordance with the program execution of the program ROM 4, and the central processing unit 3 controls the entire system.

FIG. 3 is a conventional I / O card configuration diagram. The slot connector 10 connected to the connectors 1c-1j and 2c-2j of the main rack 1 and the expansion rack 2 to interface data. And a decoder unit 11 for decoding the data of the slot connector 10 and a latch unit 12-15 for latching the output data of the decoder unit 11.

In the conventional PLC rack configured as described above, the slot connector 9 of the main CPU card is first connected to the connector 1b of the main rack 1, and the slot on connector 10 of the input / output card is connected to the main rack (1). ) And slots 9 and 10 connected to the PLC main rack 1 and the expansion rack 2 when connected to the connectors 1c-1j and 2c-2j of the expansion rack 92. The purpose of using the lines A0-A13 is to enable the enable signal of the connector 2c-2j configured in the expansion rack 2 or the main CPU card and the input / output card only on a part of the address lines A0-A13. Since it is used as a signal lamp, when the address line (A0-A13) of the card branch to be controlled is reached, only a part of the total number of address lines (A0-A13), that is, three address lines of the address lines (A0-A13) remain. As a result, you have no choice but to directly control the contacts of the input and output cards. That is, as shown in FIG. 1, the decoder unit 1k and 2k are used to select one of the eight connectors 1c-1j and 2c-2j in the main rack 1 and the expansion rack 2. In this case, the address lines A3, A4 and A5 are used, and in FIG. 2, the address line A7-A13 is used to select the main rack 1 and the expansion rack 2 by using the decoder unit 7 in FIG. All of these connectors 1c-1j and 1c-2j are connected. Therefore, it is used to find out only the address lines A0 (A1) (A2) (A6) when it is assumed that only the address lines (A0-A13) are connected to the main rack (1) and the expansion rack (2). Only lines A0-A2 allow free byte selection on any particular card.

However, since the conventional method of using a rack address line of a PLC is used only as an address connection, there is a problem in that it is not possible to use it when there is a need to exchange more data with the main CPU in the case of a special input / output card.

In view of the conventional problems, the present invention transmits a request signal for using a common RAM in a special input / output card by using a route of a general input / output contact in a main CPU first, and a central processing unit located on a special input / output card side. Receiving this signal, it suspends the original operation and sends a permission signal to the main central processing unit through the lock of the general input and output contacts, and at the same time enables the use of the common RAM in the main central processing unit. Invented to perform a plurality of functions of, when described in detail below with reference to the accompanying drawings of the present invention.

4 is a schematic configuration diagram of a PLC rack according to the present invention, in which a rack is divided into a main rack 1 and an expansion rack 2, and the main rack 1 has 14 address lines A0-A13 and two chips. A plurality of connectors 1a-1j of the selection terminals CS0 and CS1 are sequentially connected, and the decoder 1k is connected to the connector 1b, and the address line A3- is outputted from the connector 1b. After combining A5), eight connectors 1c-1j are decoded, and the expansion rack 2 has 14 address lines A0-A13 and two chip select terminals CS0-CS1. A plurality of connectors 2a-2j are sequentially connected, and a decoder 2k is connected to the connector 2b, and the address lines A3-A5 outputted from the connector 2b are combined, and then eight connectors ( 2c-2i) is decoded, and a multiplexer 21 for chip-enableing the decoder 2k is connected to the connector 2b, and the connector 2b of the expansion rack 2 is connected to the top. Forms in connection with the connector (1a) of the main rack (1).

5 is a configuration diagram of the main CPU card according to the present invention. The slot connector 9 is connected to the connector 1b of the main rack 1 to interface data, and the input address signals A13-A15 ( ) Is combined with the chip select signal generator 1 of the AND gates AN1-AN3 to generate the chip select signals CS0 (CS1) on the slot connector 9 and the program of the program ROM 4. A core unit for storing data in the RAM 5 and controlling the entire system, and decoding the address signals A0-A15 output from the main CPU 3 according to the execution. (7) and a buffer unit 6 for buffering and combining the address signals A0-A15 through the main central processing unit 3 and the decoder unit 7, respectively, and inputting them to the slot connector 9 ( And 8). FIG. 6 is a schematic diagram of a special input / output card of the present invention. As shown in FIG. A slot connector 11, a decoder unit 12 for decoding the address signals A0-A2 output from the slot connector 11 to enable the latch unit 13-16, and the slot OA gates OR1-OR4 and buffers B1 for outputting a control signal by combining the read / write signal RD WR, chip select signal CS0 and byte signal BY3 output from the connector 11; And the read / write signal generator 17 of the flip-flop FF1 and the interrupt signal INT and the fine signal FIN output from the read / write signal generator 17. Input / output central processing plant which controls the whole system and inputs to the slot connector 11 in combination with the address signals A0-A13 of the program ROM 23. (19), the transceiver 22 for transmitting and receiving 8-bit data D0-D7 output from the input / output central processing unit 19, and the data D0 output from the transceiver 22. A common RAM 21 for storing D7, an acknowledgment signal ACK output from the input / output central processing unit 19, the read / write signal generator 17 and the slot connector 11, and an interrupt. A flip-flop which is enabled according to the signal INT and the chip select signal CS1 and outputs the data D0-D7 and the read signal RD input from the transceiver 22 to the slot connector 11. 18a), the transmitter / receiver 18 comprising an OR gate OR5 and the buffer 18b and the output control signal of the transceiver 18 are chip-enabled to address (A0) of the input / output central processing unit 19. -A13), the address (A0-A13) and the read / write signal (RD) WR of the main CPU 3 input to the read / write signal RD WR and the slot connector 11). By selecting common ram (21) It consists of the multiplexer 20 stored in the memory.

Referring to the operation and effects of the present invention configured as described above are as follows.

First, as the program of the program ROM 4 is executed, the address signals A0-A13 output from the main CPU 3 are buffered through the buffer unit 6 and input to the slot connector 9. The signals A7-A13 are decoded by the decoder unit 7 and buffered through the buffer unit 8 and then combined with the output address signals A0-A13 of the buffer unit 6 to the slot connector 9. Is entered. In addition, the address signals A13-A15 outputted from the main CPU 3 ( ) Are combined in the chip select signal generator 10 to output the chip select signals CS0 and CS1 to the slot connector 9. Therefore, in the connector 1b of the main rack 1 connected to the slot connector 9, the chip select signals CS0 and CS1 and the address signals A0-A13 are output to the sequential connectors 1c-1j. In addition to being applied, they are sequentially input to the connectors 1a of the main rack 1 and the connectors 2a-2j of the expansion rack 2, and at the same time, the connectors 1c of the main rack 1 and the expansion rack 2 are applied. -1j) is inputted to the slot connector 11 of the input / output card connected to (2c-2j). At this time, the addresses A3-A5 outputted from the connector 1b of the main rack 1 are decoded by the decoder unit 1k enabled by the chip select signal Cn1 to select eight connectors 1c-1j. Done. In addition, since the address signals A7-A13 output from the connector 2b of the expansion rack 2 are selected by the multiplexer 21 and chip-enables the decoder unit 2k with the selected data, they are output from the connector 2b. After the address signals A3-A5 are decoded through the decoder 2k, eight connectors 2c-2j are selected.

On the other hand, the slot connector 9 of the main CPU card outputs an address signal A0-A13, a write signal WR, and a chip select signal S0 to the slot connector 11 to which a special input / output card is connected. In this case, the address signals A0-A3 are decoded by the decoder unit 12 configured in the special input / output card so that the byte signals BY0-BY3 chip enable the latch units 13-16, respectively, and also slots. The write signal WR, the chip select signal CS0 and the data D4 output from the connector 11 are configured in the read / write signal generator 17 and the OR gate OR1 OR2 and the flip-flop FF1. When applied to the output terminal Q1 of the flip-flop FF1, a high signal is outputted to the receive terminal of the flip-flop 18a of the transceiver 18. Since a low signal is output to the output terminal Q2 of the flip-flop 18a, the multiplexer 20 is chip-enabled. Therefore, the multiplexer 20 selects the address signals A0-A13 output from the main CPU 3 and writes them to the common RAM 21. In addition, the main CPU 3 combines the bytes BY3 configured in the special input / output card by the OR gates OR1 to OR4 of the read / write signal generator 17 and through the buffer B1. Monitoring of data D5 stops its operation until " 1 " is read in, i.e., until it receives an acknowledgment signal ACK from the I / O central processing unit 19, and the acknowledgment signal from the I / O central processing unit 19. When (ACK) is output, a high signal is output from the output terminal Q2 of the transmitter / receiver 18 so that the multiplexer 18a is chip-enabled, and the output terminal ( ), A low signal is output to enable the buffer 18b of the transceiver 18. Therefore, the address signals A0-A13, the write signal WR, and the read signal RD output from the main CPU 3 designate the addresses of the common RAM 21 through the multiplexer 20. Data (D0-D7) stored in (21) are input to the main CPU 3 through the buffer 18b of the transceiver unit 18. Then, when the main CPU 3 finishes using the common RAM 21 in the special input / output card, the use completion signal, that is, the output terminal of the flip-flop FF1 of the read / write signal generator 17 ( In this case, the high signal, that is, the fine signal (FIN) is applied to the input / output central processing unit 19, and thus the input / output central processing unit 19 receives the interrupt signal INT output from the transceiver unit 18. By stopping the use of the common RAM 21 and outputting the acknowledgment signal (ACK) to the flip-flop (18a), the output terminal (Q2) of the flip-flop (18a) is a high signal, that is, the acknowledgment signal (ACK) ) And the input / output central processing unit 19 outputs the output terminal of the flip-flop 18a ( The end signal of the common RAM 21 outputted from the signal, i.e., the fine signal FIN, is monitored and released from the interrupt.

As described in detail above, the present invention transmits a common RAM use request signal in a special input / output card by using a dominant route of general input / output contacts in the main central processing, and the central processing unit at the special input / output card side sends this signal. It sends the approved signal to the main central processing unit through the route of general input / output contacts to the main central processing unit, and at the same time, it is located in the special input / output card so that the use of the common ram can be used in the main central processing unit. Make the flip-flop output the desired signal. When the common RAM in the special I / O card of the main CPU is completed, it returns to the normal routine in order to double the data processing amount of the special I / O card of the PLC.

Claims (1)

In the main rack 1 and the expansion rack 2, in which a plurality of connectors are sequentially connected and enabled by an address signal output from the main CPU 3, the address signals of the main CPU 3 are (A13-A15) ( ), A chip select signal generator 10 for outputting the chip select signals CS0 and CS1 to the slot connector 9, and a slot connector connected to the slot connector 9 to interface data. (11), a chip select signal generator 10 for outputting read / write signals RD WR and chip select signals CS0 and CS1 of the slot connector 11, and the slot connector A slot connector 11 connected to (9) to interface data, a read / write signal RD WR, a chip select signal CS0, a byte signal BY2, and the slot connector 11; Read / write signal generator 17 for combining the data D4 and outputting another control signal, and input / output according to the interrupt signal INT and the fine signal FIN of the read / write signal generator 17. An input / output central processing unit 19 which controls the entire system of the card and inputs the slot signal 11 in combination with the address signal of the program ROM 23; A transmission / reception unit 22 for transmitting and receiving output data of the input / output central processing unit 19, a common RAM 21 for storing the output data of the transmission / reception unit 22, the input / output central processing unit 19, and reading Data which is enabled according to the acknowledgment signal ACK, the interrupt signal INT, and the chip select signal CS1 output from the recording signal generator 17 and the slot connector 11 and input from the transceiver 22. To the slot connector 11, and the chip is enabled by the output signal of the transceiver 18, the address of the input and output central processing unit 19 and the main central processing unit (3) A system for implementing multiple functions of a rack address line of a PLC, characterized by comprising a multiplexer 20 for selecting signals A0-A13 and read / write signals RD WR and storing them in the common RAM 21.