JPS61146951U - - Google Patents

Info

Publication number
JPS61146951U
JPS61146951U JP3057785U JP3057785U JPS61146951U JP S61146951 U JPS61146951 U JP S61146951U JP 3057785 U JP3057785 U JP 3057785U JP 3057785 U JP3057785 U JP 3057785U JP S61146951 U JPS61146951 U JP S61146951U
Authority
JP
Japan
Prior art keywords
logic cells
integrated circuit
master slice
slice integrated
dimensionally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3057785U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3057785U priority Critical patent/JPS61146951U/ja
Publication of JPS61146951U publication Critical patent/JPS61146951U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例のチツプレイアウト
図、第２図は本考案の他の実施例のチツプレイア
ウト図、第３図は従来のランダム論理回路のクロ
ツク回路図、第４図は従来のタコ足配線のクロツ
ク回路図である。 Ａ１，Ａ２……マスタスライスチツプ、Ｃｉｊ
……内部セル、Ｂｉｊ……専用クロツクドライブ
回路。

Claims (1)

    【実用新案登録請求の範囲】
  1. 同一チツプ上に２次元状に配された複数の論理
    セルと配線領域とを有するマスタスライス集積回
    路において、該複数の論理セルの中央の行および
    ／または列に該複数の論理セルを駆動する複数の
    クロツクドライブ回路を配列したことを特徴とす
    るマスタスライス集積回路。
JP3057785U 1985-03-04 1985-03-04 Pending JPS61146951U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3057785U JPS61146951U (ja) 1985-03-04 1985-03-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3057785U JPS61146951U (ja) 1985-03-04 1985-03-04

Publications (1)

Publication Number Publication Date
JPS61146951U true JPS61146951U (ja) 1986-09-10

Family

ID=30530400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3057785U Pending JPS61146951U (ja) 1985-03-04 1985-03-04

Country Status (1)

Country Link
JP (1) JPS61146951U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304641A (ja) * 1987-06-04 1988-12-12 Nec Corp マスタスライス方式集積回路
JPH0254950A (ja) * 1988-08-19 1990-02-23 Toshiba Corp クロック供給回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142559A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 半導体集積回路装置
JPS5914648A (ja) * 1982-07-15 1984-01-25 Nec Corp マスタスライス大規模集積回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142559A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 半導体集積回路装置
JPS5914648A (ja) * 1982-07-15 1984-01-25 Nec Corp マスタスライス大規模集積回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304641A (ja) * 1987-06-04 1988-12-12 Nec Corp マスタスライス方式集積回路
JPH0254950A (ja) * 1988-08-19 1990-02-23 Toshiba Corp クロック供給回路

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