JPS61144848A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS61144848A
JPS61144848A JP26634084A JP26634084A JPS61144848A JP S61144848 A JPS61144848 A JP S61144848A JP 26634084 A JP26634084 A JP 26634084A JP 26634084 A JP26634084 A JP 26634084A JP S61144848 A JPS61144848 A JP S61144848A
Authority
JP
Japan
Prior art keywords
film
oxide film
gate electrode
temperature
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26634084A
Other languages
Japanese (ja)
Inventor
Ryozo Nakayama
中山 良三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP26634084A priority Critical patent/JPS61144848A/en
Publication of JPS61144848A publication Critical patent/JPS61144848A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To realize an adequately thick interlayer insulating film and to prevent a gate oxide film from degradating in its voltage-withstanding capability by a method wherein a wet oxidation process is started for a gate electrode material at 850 deg.C to be ended at a temperature lower than 850 deg.C. CONSTITUTION:A field oxide film 22 is formed on an Si substrate 21 ans a P-doped polycrystalline Si film 24 is formed with the intermediately of an SiO2 film 23. The SiO2 film 23 is etched through the mask 24, and is subjected to wet oxidation involving H2 and O2. The wet oxidation starts at 850 deg.C, the temperature is caused to fall to 800 deg. at a rate of 5 deg.C/min to stay there for about 70min, whereby an approximately 650Angstrom -thick SiO2 film 25b is formed on a substrate 21 and an approximately 2,400Angstrom -thick SiO2 film 25a on the polycrystalline Si film 24. The SiO2 film 25b is subjected to etching by using NH4F, whereafter an appoximately 1,500Angstrom -thick SiO2 film 25c is retained in the vicinity of the polycrystalline Si film 24. Next, a gate oxide film 26 is provided, and a P-doped polycrystalline Si gate electrode 27 is built. Thereafter, a prescribed procedure is followed for the completion of a semiconductor device. In a device constructed as such, an interlayer insulating film is made to be thick enough with ease and a gate oxide film is protected from degradation in its voltage-withstanding feature.

Description

【発明の詳細な説明】 〔発明の技術分熱〕 本発明は半導体装置の製造方法に係り、特に電極間の絶
縁膜形成技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical aspects of the invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for forming an insulating film between electrodes.

〔発明の技術的背景〕[Technical background of the invention]

従来ダイナミックRAMのメモリセルで用いられていた
第1のpoly−Siと第2のpoly−8iの眉間絶
縁膜の形成技術の例を第3図に示す。8i基仮(1)と
第lのp017−St(3)の不純物濃度の差による酸
化レートの差、つまり不純物の濃度が濃い程,酸化速度
が速《なる事を利用して,例えば第1のpoly−st
(a)のリン濃κを濃.くシてSi基板との不純物濃度
差を大きくして、例えば850℃のWe を酸化により
第1のpoly−8Iの周囲にSt基板上よりも3倍径
膜厚の厚い酸Cヒ膜(4)を形成丁る方法がある。その
後第2のpoly−Si(5)を形成Tれば良い。
FIG. 3 shows an example of a technique for forming the first poly-Si and second poly-8i glabella insulating films conventionally used in dynamic RAM memory cells. Taking advantage of the difference in oxidation rate due to the difference in impurity concentration between the 8i group (1) and the l-th p017-St (3), that is, the higher the impurity concentration, the faster the oxidation rate, poly-st
The phosphorus concentration κ in (a) is By increasing the impurity concentration difference with the Si substrate, for example, by oxidizing We at 850°C, a thick acid carbon film (44 ). After that, a second poly-Si (5) may be formed.

しかしながらこの方法では一種類の@直でしか行なわな
いため、いろいろ問題がある。
However, since this method only uses one type of @direct, there are various problems.

まず、850℃以上では ■酸化時間が短か(して、膜厚を制御しにくい■pol
y=81の不純物濃度により膜厚が/(ラック。
First of all, at temperatures above 850°C, the oxidation time is short (so it is difficult to control the film thickness).
Due to the impurity concentration of y=81, the film thickness is /(rack.

■の一夷験結果として第4図にリン拡散の温度を950
℃、900℃で行なった後の850℃でのwet酸化に
よりpoly−81上に形成されるSiO□膜の酸比膜
厚のグラフを示す。これでわかる様にリンflkKが少
ない900℃の場合、酸化時間と酸化膜厚が直線の関係
が無くなる。
■As a result of the experiment, the temperature of phosphorus diffusion is shown in Figure 4 at 950.
5C is a graph of the acid ratio film thickness of a SiO□ film formed on poly-81 by wet oxidation at 850°C after being performed at 900°C and 900°C. As can be seen, at 900° C. where phosphorus flkK is low, there is no longer a linear relationship between oxidation time and oxide film thickness.

つまり、1ml御よ(バラツキも少なくするには、po
ly−81のリン濃度を950℃でリン拡散し高濃度に
しなければならない。しかしながら高濃度にすると ■ゲート絶allが薄(なっているため、リンのゲート
酸化膜のつきぬけによる不良や耐圧劣fヒ等の問題が発
生する。
In other words, please use 1ml (to reduce the variation,
The phosphorus concentration of ly-81 must be made high by phosphorus diffusion at 950°C. However, when the concentration is high, (2) the gate oxide film is thin, which causes problems such as defects due to phosphorus penetrating through the gate oxide film and poor breakdown voltage.

以上のために、温度を800℃以下とすると■所望の膜
厚を得るための酸化時間が長くかかり、スループットが
低く量産的でない。
For the above reasons, if the temperature is set to 800° C. or less, (1) it takes a long time to oxidize to obtain the desired film thickness, resulting in low throughput and not being suitable for mass production.

■H1と0!を燃焼する時の着火温度が低くなり、不完
全燃焼する等の危険がある。
■H1 and 0! When burning, the ignition temperature will be low and there is a risk of incomplete combustion.

〔発明の目的〕[Purpose of the invention]

本発明は上記の点に鑑みてなされたもので1層間絶縁膜
を充分に厚くしながら、膜厚を制御′しや丁く、又、ゲ
ート酸化膜の耐圧不良を無(シ、かつH,と0冨との不
完全燃焼の危険性を除く事を可能とした1間絶縁膜を形
成する方法を提供する事を目的とする。
The present invention has been made in view of the above points, and it is possible to control the film thickness while making the interlayer insulating film sufficiently thick, and also to eliminate the breakdown voltage failure of the gate oxide film. The object of the present invention is to provide a method for forming an insulating film between 1 and 2, which makes it possible to eliminate the risk of incomplete combustion between 0 and 0.

〔発明の概要〕[Summary of the invention]

本発明においては半導体基板上に絶縁膜を介してゲート
電極材料を選択的に形成した後、水素と酸素によるwe
t酸化法により850ηの温度で開始し、その後除去に
温度を下げて850℃未満の温度にしてwetQ比を終
了する。
In the present invention, a gate electrode material is selectively formed on a semiconductor substrate via an insulating film, and then a welding process using hydrogen and oxygen is performed.
We start at a temperature of 850 η with the t oxidation method and then reduce the temperature for removal to a temperature below 850° C. to end the wet Q ratio.

〔発明の効果〕〔Effect of the invention〕

本発明によれば酸「ヒ時間を短かくて、しかも膜厚を制
御しや丁くなる0例えば850℃でwet酸【ヒを開始
し、5℃/minの速度で800℃まで温度を下げ、8
00℃で形成した酸化膜の膜厚の変化を見た実験結果を
#!2図に示す、第2図に示す様に酸化時間と酸化膜厚
は非常に良い直線性をもつようIc MJ御出来る。こ
のため所望の膜厚が酸化時間で容易Ic制1111fi
来る。又、8i基板上とpoly−8L上のatヒ膜厚
比は3.5程度得られ850℃一定の時の膜厚比2.5
1ζ比べ、著しく向上する。そのためpoly−8i上
により厚い膜厚が残置出来るので。
According to the present invention, the acid deposition time can be shortened and the film thickness can be controlled. , 8
#! Experimental results looking at changes in the thickness of an oxide film formed at 00°C! As shown in FIG. 2, IcMJ can be controlled so that the oxidation time and oxide film thickness have very good linearity. Therefore, it is easy to obtain the desired film thickness by changing the oxidation time.
come. Also, the film thickness ratio on the 8i substrate and on the poly-8L is about 3.5, and the film thickness ratio at a constant temperature of 850°C is 2.5.
Significant improvement compared to 1ζ. Therefore, a thicker film can be left on the poly-8i.

8i基板と1polyrVIeあるいは1 polyと
2poly間の耐圧が向上し、半導体素子の信頼性が向
上する。
The breakdown voltage between the 8i substrate and 1polyrVIe or between 1poly and 2poly is improved, and the reliability of the semiconductor device is improved.

またl polyのリンIlKを濃くする必要がないの
で、例えばリン拡散の温度を低く、また拡散時間を短か
くする事が出来るので、1poly下の絶縁膜が薄くな
りても、不純物(リン)が絶縁膜をつきぬけてSt基板
に達してしまい、ゲート耐圧不良を発生する−をいう現
像も防止する事が出来る。
In addition, since there is no need to increase the concentration of phosphorus IlK in l poly, it is possible to lower the phosphorus diffusion temperature and shorten the diffusion time, so even if the insulating film under l poly becomes thinner, impurities (phosphorus) can be It is also possible to prevent development that would penetrate through the insulating film and reach the St substrate, causing gate breakdown voltage failure.

又、燃焼酸「ヒ開始のHlと08の反応も反応が安定で
ある比較的高温(例えば850℃以上)で行なえるため
1作業の安全が保てる。
In addition, the reaction between H1 and 08, which is initiated by the combustion acid, can be carried out at a relatively high temperature (for example, 850° C. or higher) where the reaction is stable, so the safety of one operation can be maintained.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1因を用いて説明する。 An embodiment of the present invention will be explained using the first factor.

まず、Si基板(21)上に選択約6こフィールド酸化
膜(22)を形成した後、例”えば120A程度の1s
t酸化膜(23)を介して選択的に例えば900℃、3
0分。
First, after forming about 6 selected field oxide films (22) on the Si substrate (21),
For example, 900° C., 3
0 minutes.

でpocj @を用いたリン拡散により(P)を拡散し
た膜厚4000Å程度の1st poly−8i(24
)を形成する。
1st poly-8i (24
) to form.

(第1図象)次に必要ならば1 st poly−8i
(24)をマスクに1stゲート酸化膜(23)をエツ
チングしても良い。
(1st image) Next, if necessary, 1st poly-8i
The first gate oxide film (23) may be etched using (24) as a mask.

次tこ例えばH5と0□を含むwet酸比を行ないその
時の温度はまず850℃でwst酸化を開始して5’C
/minで炉の@度を除去に下げ、800℃にまで下げ
、その後800℃を一定に保りて、約70分、we を
酸比する事により、81基板上Iこ約650人の8i0
z膜(25(b) ) 、 po 1 y−8i上Iこ
約240(lのst□、膜(25(R>)を形成Tる。
Next, perform a wet acid ratio containing, for example, H5 and 0
By lowering the temperature of the furnace to 800°C and then keeping the temperature constant at 800°C for about 70 minutes, the 8i0 temperature of about 650 people on 81 substrates was
z film (25(b)), on po 1 y-8i I about 240(l st□, form a film (25(R>)).

(第1図b)次Iζ例えばNl(、Fを用いて8tQ□
膜(25(b) )を、エツチングTる。その時1 s
t poly−8iの問題のみに約250A程度の8i
0象膜(25(c) )が残置される。
(Fig. 1b) For example, using Nl(, F, 8tQ□
The film (25(b)) is etched. At that time 1 s
8i of about 250A only for the problem of poly-8i
The zero quadrant (25(c)) is left behind.

(第1図C) その後、約250A程度の2 ndゲート酸化膜(26
)を形成後1例えばリンを拡散したpoly−8iで2
ndゲート電極(27)を選択的に形成Tる。(第1図
d)その後従来技術によりダイナミックに4jAM等の
午導体装置を製造する・ 〔発明の他の実施例〕 上記実施例ではS1基板上の8iQ1膜(25(b) 
)を除去した後に2 ndゲート酸化膜(26)を形成
したが、  1 st poly−81上の113iQ
、膜と2ndゲート酸化膜を同時に形成しても良い。例
えば、2ndゲート酸化膜を300A程度に丁れば、p
oly−8i上には1200ん程度形成出来、しかもS
t基板上の8 IQ。
(Figure 1C) After that, a 2nd gate oxide film (26
) After forming 1, for example, 2 with phosphorus-diffused poly-8i.
A nd gate electrode (27) is selectively formed. (FIG. 1d) Then, a 4jAM or other conductor device is dynamically manufactured using conventional techniques. [Other embodiments of the invention] In the above embodiment, an 8iQ1 film (25(b)
) was removed, the 2nd gate oxide film (26) was formed, but the 113iQ on the 1st poly-81
, and the second gate oxide film may be formed simultaneously. For example, if the 2nd gate oxide film is set to about 300A, p
About 1200 molecules can be formed on oly-8i, and S
8 IQ on t substrate.

膜(25(b) )のエツチング工程が入らないので、
1stpoly−8i周辺端でのSiQ、膜(25(a
) )の膜厚の減少が起こらな(て済むので1st p
oly−8iと2ndゲ一ト電極間の耐圧(絶縁性)が
向上し、高信頼性が実現出来る。
Since there is no etching process for the film (25(b)),
SiQ at the peripheral edge of 1stpoly-8i, film (25(a
) Since the decrease in film thickness of ) does not occur, the 1st p
The withstand voltage (insulation) between oly-8i and the 2nd gate electrode is improved, and high reliability can be achieved.

又、このwet酸化前後に他の雰囲気ガス例えばdry
ol、ArあるいはN!等の熱処理を行なりても良い。
Also, before and after this wet oxidation, other atmospheric gases such as dry
ol, Ar or N! Heat treatment such as the following may also be performed.

例えば、ウェハーの温度が炉の中で安定になるまでN、
雰囲気にしておく事により、酸化は進まないで済むので
、膜厚の制御も良くなる。また高温でのdr7Q1等を
行なう事によりて%StO,の耐圧が向上する。
For example, N until the wafer temperature stabilizes in the furnace.
By keeping the film in an atmosphere, oxidation does not proceed, and the film thickness can be controlled better. Further, by performing dr7Q1 etc. at high temperature, the withstand voltage of %StO is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の工程断面図、第2図は本発
明の850℃から800℃に炉温度を低下させて’we
t酸化した時酸化速度の一実験結果の特性図、第3図は
従来の工程断面図、第4図は従来850℃でのwet酸
化の酸化速度の一実験結果を示す特性図である。 図において。 1.21・−St基板、2,4,23,22゜25.2
6−8i0.膜、3.24・・・1st poly −
8i、5.27−2ndゲート電11 (2nd po
ly−8i)。 代理人弁理士  則 近 憲 佑(他1名)第  1 
図 第2図 杉(ジLウニブト鍜イヒ時肉 85v啼8ρo’c 第3図 第  4 図 B5o’c
Fig. 1 is a cross-sectional view of the process of one embodiment of the present invention, and Fig. 2 is a process cross-sectional view of one embodiment of the present invention.
FIG. 3 is a cross-sectional view of a conventional process, and FIG. 4 is a characteristic diagram showing experimental results of oxidation speed in wet oxidation at 850° C. In fig. 1.21・-St substrate, 2, 4, 23, 22° 25.2
6-8i0. Membrane, 3.24...1st poly −
8i, 5.27-2nd gate electrode 11 (2nd po
ly-8i). Representative Patent Attorney Kensuke Chika (and 1 other person) No. 1
Figure 2 Cedar

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜を介してゲート電極材料を
選択的に形成した後、半導体基板およびゲート電極材料
を酸化する場合、少なくとも水蒸気を含む水蒸気中で、
かつ第1の温度で開始して第1の温度より低い第2の温
度まで低下させて行なう様な酸化熱処理を行なう事によ
り、前記半導体基板表面よりも前記ゲート電極材料表面
の酸化膜が厚くなる様にする事を特徴とする半導体装置
の製造方法。
(1) When oxidizing the semiconductor substrate and gate electrode material after selectively forming the gate electrode material on the semiconductor substrate via an insulating film, in water vapor containing at least water vapor,
and by performing an oxidation heat treatment that starts at a first temperature and lowers it to a second temperature lower than the first temperature, the oxide film on the surface of the gate electrode material becomes thicker than on the surface of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized by:
(2)ゲート電極材料を多結晶シリコンを用いて、半導
体基板表面よりも多結晶シリコン表面の不純物濃度が濃
く、かつ第1の温度を850℃以下で行なう事を特徴と
する前記特許請求の範囲第1項記載の半導体装置の製造
方法。
(2) The above-mentioned claim is characterized in that polycrystalline silicon is used as the gate electrode material, the impurity concentration of the polycrystalline silicon surface is higher than that of the semiconductor substrate surface, and the first temperature is 850° C. or lower. 2. A method for manufacturing a semiconductor device according to item 1.
(3)熱処理後、前記半導体基板表面の熱酸化膜を除去
する事により、前記ゲート電極材料表面のみに熱酸化膜
を残置させる工程を含む事を特徴とする前記特許請求の
範囲第1項又は第2項記載の半導体装置の製造方法。
(3) The method includes the step of leaving a thermal oxide film only on the surface of the gate electrode material by removing the thermal oxide film on the surface of the semiconductor substrate after heat treatment, or 2. The method for manufacturing a semiconductor device according to item 2.
JP26634084A 1984-12-19 1984-12-19 Manufacture of semiconductor device Pending JPS61144848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26634084A JPS61144848A (en) 1984-12-19 1984-12-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26634084A JPS61144848A (en) 1984-12-19 1984-12-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61144848A true JPS61144848A (en) 1986-07-02

Family

ID=17429573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26634084A Pending JPS61144848A (en) 1984-12-19 1984-12-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61144848A (en)

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