JPS609118A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS609118A JPS609118A JP11745983A JP11745983A JPS609118A JP S609118 A JPS609118 A JP S609118A JP 11745983 A JP11745983 A JP 11745983A JP 11745983 A JP11745983 A JP 11745983A JP S609118 A JPS609118 A JP S609118A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- impurity
- source layer
- layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 44
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000001301 oxygen Substances 0.000 claims abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- 230000032683 aging Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 23
- 238000011109 contamination Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.
現在、電力用トランジスタのペース層の形成は、その不
純物濃度を均一化するだめに、イオン注入法により半導
体基板内にこれと反対導電形の拡散不純物を導入して、
高イ農度の拡散不純物源層を形成することにより行われ
ている。例えばＮＰＮ ）ランジスタを例に誉げると、
第１図（Ａ）乃至同図（Ｆ）に示す工程により製造され
ている６、先ず、同図（〜に示す如く、表面領域にＮ−
ＩＱｌを形成しだ半導体基板２を用）５する１１次に、
同図（Ｂ）に示す如く、Ｎ一層１０表面領域に〜１．Ｏ
Ｘ １０１５／ｃｄｌの注入量でＰ形の不純物を注入１
〜、深さ約〜０，６ｔｔｍの高濃度の拡散不純物源層３
を形成する。次いで、拡散不純物源層３の外部拡散を防
止するために、気相成長法により酸化膜４全同図（Ｃ）
に示す如く、形成する。これに約１０ （）０℃の窒素
雰囲気で数時間スラツピングを施し、拡散不純物源層３
′の拡散深さを約２μｍ深くする。これは、後述のエミ
ッタ用拡散マスクを形成する際の熱処理によって、拡散
不純物源層３′中の不純物濃度が低下するのを防止する
ためである。次に、同図■）に示す如く、エミッタ用拡
散マスクとなる熱酸化膜５を酸化膜４及び半導体基板２
の露出した裏面側に形成する。Currently, in order to make the impurity concentration uniform in forming the base layer of power transistors, diffused impurities of the opposite conductivity type are introduced into the semiconductor substrate by ion implantation.
This is done by forming a diffusion impurity source layer with a high concentration of impurities. For example, if we take NPN) transistor as an example,
6 manufactured by the steps shown in FIGS. 1(A) to 1(F). First, as shown in FIG.
11 Next, use the semiconductor substrate 2 to form the IQl.
As shown in the same figure (B), ~1. O
P-type impurity implantation 1 with an implantation amount of X 1015/cdl
~, a high concentration diffused impurity source layer 3 with a depth of approximately ~0.6ttm
form. Next, in order to prevent external diffusion of the diffusion impurity source layer 3, the entire oxide film 4 is grown by vapor phase growth method (FIG. 1C).
Form as shown. This was subjected to slapping for several hours in a nitrogen atmosphere at approximately 10 ()0°C, and the diffused impurity source layer 3
The diffusion depth of ' is increased by approximately 2 μm. This is to prevent the impurity concentration in the diffused impurity source layer 3' from decreasing due to heat treatment when forming an emitter diffusion mask, which will be described later. Next, as shown in FIG.
Formed on the exposed back side of the
然る後、これに１２５０℃で数時間スランビングを施し
、拡散不純物源層３′からの拡散により拡散深さが約３
０μｍのベースＲ′ｉ６を同図（Ｆ）に示す如く形成す
る。この後、エミッタ拡散処理、電極形成処理等を行い
所望の半導体装置を得る。Thereafter, this was subjected to slumping at 1250°C for several hours, and the diffusion depth was increased to about 3 by diffusion from the diffused impurity source layer 3'.
A base R'i6 of 0 μm is formed as shown in FIG. Thereafter, emitter diffusion treatment, electrode formation treatment, etc. are performed to obtain a desired semiconductor device.
このような従来の半導体装置の製造方法では、次のよう
な問題がある。Such conventional semiconductor device manufacturing methods have the following problems.
（リ 拡散不純物源層３の外部拡散を防止するだめ酸化
膜４は、通常常圧ＣＶＤ法、連続ＣＶＤ法等により形成
されるため、大Ｍ１・生産に不向きであり、生産性の向
上を達成できない。(Re) The oxide film 4 that prevents external diffusion of the diffusion impurity source layer 3 is usually formed by atmospheric pressure CVD, continuous CVD, etc., and is not suitable for large M1 production. Can not.
■ また、高品質の１欧化膜４を得ることができないた
め、歩留シを向上させることができない。酸化膜４の品
質を高めることができないのは、例えばＣＶＤ法による
酸化膜４の場合には、５ｔ）（４＋ｏ２→５ｉ０２ ＋
２Ｈ１の反応によってヒロックと称せられるシラン酸
化物が発生するため、その付着或は酸化膜４中にピンホ
ールが発生し易いからである。更に、不純物を含むＣＶ
Ｄ酸化膜、ＰＳＧ膜、ＢＳＧ膜を形成する工程と併用１
〜で酸化膜４が形成されるため、ＰＳＧ膜を形成する際
のＰＨ８，ＢＳＧ膜を形成する際のＢ、Ｈ，ｉｆスによ
って汚染を受け易いからである。(2) Moreover, since it is not possible to obtain a high-quality monomer film 4, the yield cannot be improved. The reason why the quality of the oxide film 4 cannot be improved is, for example, in the case of the oxide film 4 made by the CVD method, 5t)(4+o2→5i02+
This is because silane oxides called hillocks are generated by the 2H1 reaction, and pinholes are likely to occur in the oxide film 4 or in the adhesion of silane oxides. Furthermore, CV containing impurities
Combined use with the process of forming D oxide film, PSG film, BSG film 1
This is because, since the oxide film 4 is formed in ~, it is easily contaminated by PH8 when forming the PSG film and B, H, if gas when forming the BSG film.
本発明は、半導体基板内に形成する不純物領域の表面濃
度を均一にし、かつ、高歩留シで生産性の向上を達成し
た半導体装置の製造方法を提供することをその目的とす
るものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that makes the surface concentration of an impurity region formed in a semiconductor substrate uniform and achieves high yield and improved productivity. .
本発明は表面に厚肉の酸化膜を形成した拡散不純物源層
から、１０００〜１１００℃の窒素雰囲気中で所定の拡
散深ざの不純物領域を半導体基板内に延出させた後、こ
れに熱酸化及び１？００〜１３００℃のスランビング処
理を施す工程を設けたことにより、半導体基板内に形成
する不純物領域の表面濃度を均一にし、かつ、歩留り及
び生産性の向上を達成［また半導体装置の製造方法であ
る。In the present invention, an impurity region with a predetermined diffusion depth is extended into a semiconductor substrate from a diffused impurity source layer with a thick oxide film formed on the surface in a nitrogen atmosphere at 1000 to 1100°C, and then heated. By providing a process of oxidation and slumbing treatment at 100 to 1300 degrees Celsius, the surface concentration of the impurity region formed in the semiconductor substrate is made uniform, and yield and productivity are improved. This is the manufacturing method.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
先ず、第２図（Ａ）に示す如く、表面領域にＮ一層１０
を形成した半導体基板１１を用意する。次いで、同図（
Ｂ）に示す如り、Ｎ一層の表面領域に〜１、 ＯＸ １
０”／ｃＪの注入量でＰ形の不純物を注入し、深さ約〜
０．６１１ｍの高θ度の不純物拡散源層１２を形成する
。次に、同図（Ｃ）に示す如く、これに１０００〜１１
００℃の乾燥酸素雰囲気中で酸化処理を施し、厚さ約３
０００Ｘの厚肉の酸化Ｍ１３を不純物拡散源層Ｊ２上及
び半導体基板１ノの裏面上に形成する。次いで、同図の
）に示す如く、これに例えば１０００℃の温度で窒素雰
囲気中で数時間スランビング処理を施し、拡散深さが約
３μｍの不純物領域１４を不純物拡散源層１２の不純物
拡散によって形成する。次に、これに同図の）に示す如
く、酸化性雰囲気中で熱酸化を施し、酸化膜１３上に後
述するエミッタ用拡散マスクとなる熱酸化膜１５を一体
に形成する。然る後、１２ （ｌ ０〜１３００℃の温
度範囲にある温度、例えば１２５０℃で数十時間スラン
ビング処理を施し、同図（ド）に示す如く、拡散保さが
約３０ｔ１ｍのペース層１６をＮ一層ノθ中に形成する
っこの後、熱酸化膜１５にエミッタ拡散用の窓を開口し
、エミッタ拡散等の処理を経て半導体装置２０を得る。First, as shown in FIG. 2(A), a layer of N 10
A semiconductor substrate 11 having a structure formed thereon is prepared. Next, the same figure (
As shown in B), in the surface area of the N single layer ~1, OX1
P-type impurities are implanted at an implantation dose of 0"/cJ to a depth of approximately ~
An impurity diffusion source layer 12 with a high θ degree of 0.611 m is formed. Next, as shown in the same figure (C), 1000 to 11
Oxidation treatment is performed in a dry oxygen atmosphere at 00℃, and the thickness is approximately 3.
A thick oxide M13 of 000X is formed on the impurity diffusion source layer J2 and the back surface of the semiconductor substrate 1. Next, as shown in ) in the same figure, this is subjected to a slumping treatment for several hours in a nitrogen atmosphere at a temperature of, for example, 1000° C., and an impurity region 14 with a diffusion depth of about 3 μm is formed by impurity diffusion in the impurity diffusion source layer 12. do. Next, as shown in ) in the same figure, thermal oxidation is performed in an oxidizing atmosphere to integrally form a thermal oxide film 15 on the oxide film 13, which will serve as a diffusion mask for an emitter to be described later. Thereafter, a slumping treatment is performed at a temperature in the temperature range of 0 to 1,300 degrees Celsius, for example, 1,250 degrees Celsius, for several tens of hours to form a paste layer 16 with a diffusion retention of about 30 tons, as shown in FIG. After forming the N layer in θ, a window for emitter diffusion is opened in the thermal oxide film 15, and a semiconductor device 20 is obtained through processes such as emitter diffusion.
２このようにこの半導体装置の製造方法によれば、拡散
不純物源層１２の外部拡散を防止する酸化膜１３は、熱
酸化法にて形成されるので、量産が容易であり、生産性
を向上させることができる１、しかも、この酸化膜１３
の形成の際には、不純物が混入し易いＰＳＧ膜等の形成
処理は併用されないので、はとんど汚染のない清浄な酸
化膜１３を形成して、後続のスランビング処理によって
極めて高品質のペース層１６を形成することができる。2 As described above, according to this semiconductor device manufacturing method, the oxide film 13 that prevents the diffusion of the diffused impurity source layer 12 to the outside is formed by a thermal oxidation method, which facilitates mass production and improves productivity. 1, and this oxide film 13
When forming the oxide film 13, a process for forming a PSG film, etc., which easily contains impurities, is not used, so a clean oxide film 13 with almost no contamination is formed, and the subsequent slumping process produces an extremely high quality paste. Layer 16 can be formed.
更に、酸化膜１３の形成が１０００〜１１００℃の高温
度で、かつ、数時間の長時間加熱によって行われるので
、次のスランピング効果ヲ促進することによって、ベー
ス層１６を形成するだめの不純物濃度の低下を防止して
、汚染度の小さいベース層１６が形成される。Furthermore, since the oxide film 13 is formed at a high temperature of 1,000 to 1,100° C. and by heating for several hours, the impurity concentration for forming the base layer 16 can be reduced by promoting the next slumping effect. A base layer 16 with a low degree of contamination is formed by preventing a decrease in the contamination.
因に、このようにして得らｔまた半導体装置のベース層
１６形成後における耐圧歩留シを調べると、シート抵抗
のばらつき幅（ΔρＳ）を±４％に抑えた半導体基板１
ノを用いた場合、エミッタ開放コレクク降伏電圧（’Ｖ
ｃｎｏ）について見ると従来５０％のＶＣＢＯ歩留りを
実施例によるものでは９５％ＶＣＲＯ歩留まで向上させ
ることができた。Incidentally, when examining the breakdown voltage yield after forming the base layer 16 of the semiconductor device obtained in this way, it was found that the semiconductor substrate 1 with the sheet resistance variation range (ΔρS) suppressed to ±4%
When using , the emitter open-collection breakdown voltage ('V
Regarding cno), the conventional VCBO yield was 50%, but the embodiment was able to improve the VCRO yield to 95%.
なお、実施例でけＮ−ＰＮ型のベース層１６の形成に本
発明を適用したものについて説明したが、この他にも、
イオン注入後に熱酸化工程を有する工程、例えばＰＮＰ
型トランジスタのエミッタ形成やＮＰＮ型トランジスタ
のコンタクトＰ十形成などにも適用できることは勿論で
ある。In addition, although the present invention has been described in the embodiment to form the N-PN type base layer 16, there are other methods as well.
A process that includes a thermal oxidation process after ion implantation, e.g. PNP
It goes without saying that the present invention can also be applied to the formation of an emitter of a type transistor or the formation of a contact P1 of an NPN type transistor.
以上説明した如く、本発明に係る半導体装置の製造方法
によれば、半導体基板内に形成する不純物領域の表面濃
度を均一にし、かつ、歩留り及び生産性の向上を達成で
きる等顕著な効果を奏するものである。、As explained above, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to make the surface concentration of an impurity region formed in a semiconductor substrate uniform, and to achieve remarkable effects such as improving yield and productivity. It is something. ,
第１図（Ａ）乃至同図（Ｆ）は、従来の半導体装置の製
造方法を工程順に示す説・門口、第２図（Ａ）乃至同図
（Ｆ）は、本発明方法を工程順に示す説明図である。
１０・・・Ｎ一層、１ノ・・・半導体基板、１２・・・
不純物拡散源層、１３・・・酸化膜、１４・・不純物領
域、１５・・・熱酸化膜、１６・・・ベース層、２０・
・・半導体装置。1(A) to 1(F) show a conventional method for manufacturing a semiconductor device in the order of steps, and FIGS. 2(A) to 2(F) show the method of the present invention in the order of steps. It is an explanatory diagram. 10...N single layer, 1no...semiconductor substrate, 12...
Impurity diffusion source layer, 13... Oxide film, 14... Impurity region, 15... Thermal oxide film, 16... Base layer, 20...
...Semiconductor devices.
Claims (1)
該拡散不純物源層から所定の拡散深さの不イ′口物領域
を形成する工程を具備する半導体装置の製造方法におい
て、不純物領域の形成］−程を、１０００〜１１００℃
の酸素芽囲気中で厚肉の酸化膜を拡散不純物源層上に形
成した後、１０００〜１１００℃の窒素雰囲気中で該拡
散不純物源層が所定の拡散深さの不純物領域を半導体基
板内に延出させ、次いで、これに熱歳化を施しＺＣ後１
２００〜１３００℃のスラツピング処理を施す工程とし
たことを特徴とする半導体装置の製造方法。After forming a diffused impurity source layer on a semiconductor substrate of one conductivity type,
In the method for manufacturing a semiconductor device comprising the step of forming an impurity region having a predetermined diffusion depth from the diffused impurity source layer, the step of forming the impurity region is performed at 1000 to 1100°C.
After forming a thick oxide film on the diffused impurity source layer in an oxygen atmosphere of 1000°C to 1100°C, the diffused impurity source layer forms an impurity region with a predetermined diffusion depth in the semiconductor substrate in a nitrogen atmosphere of 1000 to 1100°C. It was extended and then subjected to heat aging and after ZC 1
A method for manufacturing a semiconductor device, comprising a step of performing slapping treatment at 200 to 1300°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11745983A JPS609118A (en) | 1983-06-29 | 1983-06-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11745983A JPS609118A (en) | 1983-06-29 | 1983-06-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS609118A true JPS609118A (en) | 1985-01-18 |
Family
ID=14712192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11745983A Pending JPS609118A (en) | 1983-06-29 | 1983-06-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609118A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH677558A5 (en) * | 1988-11-28 | 1991-05-31 | Asea Brown Boveri | Deep PN junction mfr. for power thyristor - has oxide layer applied to surface of substrate during diffusion process for doping material |
-
1983
- 1983-06-29 JP JP11745983A patent/JPS609118A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH677558A5 (en) * | 1988-11-28 | 1991-05-31 | Asea Brown Boveri | Deep PN junction mfr. for power thyristor - has oxide layer applied to surface of substrate during diffusion process for doping material |
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