JPS61144046A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61144046A
JPS61144046A JP59267946A JP26794684A JPS61144046A JP S61144046 A JPS61144046 A JP S61144046A JP 59267946 A JP59267946 A JP 59267946A JP 26794684 A JP26794684 A JP 26794684A JP S61144046 A JPS61144046 A JP S61144046A
Authority
JP
Japan
Prior art keywords
semiconductor chip
waveshape
chip
crests
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59267946A
Other languages
Japanese (ja)
Other versions
JPH0141265B2 (en
Inventor
Tsuneo Hashizume
橋詰　恒雄
Hirotsugu Harada
原田　曠嗣
Hirobumi Ikeo
池尾　寛文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59267946A priority Critical patent/JPS61144046A/en
Publication of JPS61144046A publication Critical patent/JPS61144046A/en
Publication of JPH0141265B2 publication Critical patent/JPH0141265B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To prevent an element on the surface from damaging due to a shrinkage at sealing resin curing time by forming a die pad in a waveshape having a plurality of crests, and securing to braze semiconductor chips to the crests with the longitudinal direction in the waveshape direction. CONSTITUTION:A die pad 11 is formed to have a square waveshape having a plurality of crests 11a. A semiconductor chip 1 has 3mm or less of sides in a rectangular shape having 3mm or longer of long side so that the longitudinal direction is in the waveshape direction, and secured to be brazed to the crests 11a. The electrode pads 4 and external leads 5 of the chip 1 are wire bonded by fine metal wirings 6, and the chip 1 is sealed with resin sealer 7 by resin injection molding. When the sealing resin is shrinked by curing, the pad 11 becomes waveshape to have large flexibility. Thus, it does not disturb the shrinkage of the chip 1 but respond thereto.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ダイパッドに半導体チップを固着し、樹脂
封止した半導体装［ｔＫ関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device [tK] in which a semiconductor chip is fixed to a die pad and sealed with resin.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体装置は、第２図に断面図で示すよ
うになっていた。（１）はシリコン材などからなる半導
体チップで、リードフレームのダイパッド（２）上にろ
う材（３）により接合固着されている。A conventional semiconductor device of this type has a cross-sectional view shown in FIG. (1) is a semiconductor chip made of silicon material or the like, which is bonded and fixed onto a die pad (2) of a lead frame with a brazing material (3).

ろう材（３）には金−シリコン、銀ペースト又けはんだ
などを用いて−る。こうして、半導体チップ（１）の発
熱がダイパッド（２）に伝達放散されるようにしている
。半導体チップ（１）上の電極パッド（４）と外部リー
ド（５）とを、金属細線（６）でワイヤボンディングし
ている。（７）は注型成形によシ半導体チップ（１）部
を封止した樹脂封止体である。Gold-silicon, silver paste, solder, etc. are used as the brazing material (3). In this way, the heat generated by the semiconductor chip (1) is transmitted to and dissipated from the die pad (2). Electrode pads (4) on a semiconductor chip (1) and external leads (5) are wire-bonded using thin metal wires (6). (7) is a resin sealing body in which the semiconductor chip (1) portion is sealed by cast molding.

上記従来の装置において、注型された封止樹脂が硬化時
に収縮する。半導体チップ（１）はダイパッド（２）上
に全面で接着されているが、上記樹脂の収縮に対し、半
導体チップ（１）が小さく、チップ面の配線パターンも
３μｍ以上あって比較的集積度が高くなｈ場合は、問題
とはならなかった。In the conventional apparatus described above, the cast sealing resin contracts when it hardens. The semiconductor chip (1) is bonded on the entire surface of the die pad (2), but due to the shrinkage of the resin, the semiconductor chip (1) is small and the wiring pattern on the chip surface is 3 μm or more, so the degree of integration is relatively low. In the case of high h, there was no problem.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の半導体装置では、半導体チップ（１
）の長辺が５ｍｍを超え、配線パターンが３）ｔｒｎよ
ｐ小さくなった場合は、半導体チップ（１）に形成され
である個別要素も小さくなる。この場合、封止樹脂の硬
化時の収縮により、半導体チップ（１）は水平方向の圧
縮力を受ける。しかし、下面は剛性の大きいダイパッド
（２）に全面接着されていて収縮が阻止される。半導体
チップ（１）表面に接している封止樹脂が中心に向って
収縮するが、このとき、半導体チップ（１）の辺が短い
と問題にはならないが、辺が長いと中心から距離が遠い
周辺側では封止樹脂が収縮によ〕動く度合いが大きくな
る。この収縮移動をする封止樹脂に接した、半導体チッ
プ（１）周辺部でのアルミなどの配線などが、変形など
の損傷を受ける問題点があった。また、さらに、半導体
チップ（１）にパッシベーション（図示は略す）を施し
である場合は、このパッシベ−ションにクラックを生じ
、防湿が阻害され湿気の浸入によシミ気持性不良となる
などの問題点があった。In the conventional semiconductor device as described above, a semiconductor chip (1
) exceeds 5 mm and the wiring pattern becomes smaller than 3) trn, the individual elements formed on the semiconductor chip (1) also become smaller. In this case, the semiconductor chip (1) is subjected to a compressive force in the horizontal direction due to contraction of the sealing resin when it hardens. However, the lower surface is entirely bonded to the highly rigid die pad (2), preventing shrinkage. The sealing resin that is in contact with the surface of the semiconductor chip (1) contracts toward the center. At this time, if the sides of the semiconductor chip (1) are short, there is no problem, but if the sides are long, the distance from the center is far. On the peripheral side, the degree of movement of the sealing resin due to contraction increases. There is a problem in that wiring made of aluminum or the like in the periphery of the semiconductor chip (1), which is in contact with the shrinking and moving sealing resin, may be damaged such as deformation. Additionally, if the semiconductor chip (1) is passivated (not shown), cracks may occur in the passivation, inhibiting moisture protection and causing moisture ingress, resulting in poor stain resistance. There was a point.

この発明は、このような問題点を解決するためＫなされ
たもので、封止樹脂の硬化時の収縮による半導体チップ
の表面部の要素の損傷をなくし、品質を向上した半導体
装置を得ることを目的としている。特に１半導体チップ
が長方形をなし、短辺が３ｍｍ以下で長辺が３ｍｍを超
える場合に好適である。This invention was made to solve these problems, and aims to eliminate damage to elements on the surface of a semiconductor chip due to shrinkage when the sealing resin hardens, and to obtain a semiconductor device with improved quality. The purpose is This is particularly suitable when one semiconductor chip has a rectangular shape, and the short side is 3 mm or less and the long side is over 3 mm.

〔問題点を解決するための手段〕[Means for solving problems]

この発明にかかる半導体装置は、ダイパッドを複数の山
部をもつ波形に形成し、半導体チップを長手方向を波形
の方向にして各山部上にろう付け固着したものである。In a semiconductor device according to the present invention, a die pad is formed in a wave shape having a plurality of peaks, and a semiconductor chip is fixed to each peak by brazing with the longitudinal direction of the die pad in the direction of the waveform.

〔作用〕[Effect]

封止樹脂が硬化により収縮すると、半導体チップに圧縮
力が加わるが、最も影響の大きい長辺方向く対しては、
ダイパッドが波形をなしていてたわむことができるので
、半導体チップは抑制されずに封止樹脂の収縮に順応し
て縮むことができる。When the encapsulant resin contracts due to curing, compressive force is applied to the semiconductor chip, but in the long side direction, where the effect is greatest,
Since the die pad has a corrugated shape and can be bent, the semiconductor chip can shrink unrestrictedly to accommodate the shrinkage of the encapsulating resin.

〔実施例〕〔Example〕

第１図はこの発明による半導体装置の一実施例の要部の
拡大断面図である。αＤはダイパッドで、複数の山％Ｄ
ｌａ）をもつ角形の波形に形成されている。半導体チッ
プ（１）は短辺が３ｍｍ以下で、長辺が３ｍｍを超えた
長方形であり、長手方向を波形の方向圧し、各山部（ｌ
ｌａ）上にろう付け固着している。半導体チップ（１）
の各電極パッド（４）と外部リード（５）とを金属細線
（６）でワイヤポンディングしている。この半導体チッ
プ（１）部を樹脂の注型成形による樹脂封止体（７）で
封止している。FIG. 1 is an enlarged sectional view of a main part of an embodiment of a semiconductor device according to the present invention. αD is a die pad with multiple peaks %D
It is formed into a rectangular waveform with 1a). The semiconductor chip (1) has a rectangular shape with a short side of 3 mm or less and a long side of over 3 mm.
la) It is fixed by brazing on the top. Semiconductor chip (1)
Each electrode pad (4) and the external lead (5) are wire bonded with a thin metal wire (6). This semiconductor chip (1) portion is sealed with a resin sealing body (7) formed by resin casting.

上記一実施例の＃ｆｌＫ：おいて、封止樹脂が硬化によ
り収縮すると、半導体チップ（１）が圧縮力を受けて中
心に向って収縮しようとする。半導体チップ（１）を接
着しているダイパッド（ロ）は、波形になっていて、た
わみ性が大きく、半導体チップ（１）の収縮を阻害する
ことなく、順応させる。これにより封止樹脂が中心部に
向って収縮しても、半導体チップ（１）も順応して収縮
され、表面部の周辺部の要素が損傷を受けることがない
。また、半導体チップ（１）部にパッシベーションが施
されである場合は、パッシベーションのクラック発生が
防止される。In #flK of the above embodiment, when the sealing resin contracts due to curing, the semiconductor chip (1) receives compressive force and tends to contract toward the center. The die pad (b) to which the semiconductor chip (1) is bonded has a corrugated shape and is highly flexible, allowing the semiconductor chip (1) to conform to shrinkage without inhibiting it. As a result, even if the sealing resin shrinks toward the center, the semiconductor chip (1) also shrinks accordingly, and elements on the periphery of the surface are not damaged. Furthermore, if the semiconductor chip (1) portion is passivated, cracks in the passivation are prevented from occurring.

なお、上記実施例ではダイパッドαｐの波形は角形にし
たが、円弧状にしてもよ匹。In the above embodiment, the waveform of the die pad αp is rectangular, but it may also be arcuate.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、ダイパッドを複数の
山部をもつ波形に形成し、半導体チップを長手方向を波
形の方向にして各山部上にろう付け固着したので、封止
樹脂の硬化時の収縮による半導体チップの表面部の要素
の損傷が防止され、品質を向上することができる。As described above, according to the present invention, the die pad is formed into a corrugated shape having a plurality of peaks, and the semiconductor chip is brazed and fixed onto each peak with the longitudinal direction of the waveform. Damage to the surface elements of the semiconductor chip due to shrinkage during curing is prevented, and quality can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明による半導体装置の一実施例の要部の
拡大断面図、第２図は従来の半導体装置の断面図である
。 １・・・半導体チップ、３・・・ろう材、７・・・樹脂
封止体、　１１・・・ダイパッド、ｌｌａ・・・山部な
お、図中同一符号は同−又は相当部分を示す。FIG. 1 is an enlarged sectional view of a main part of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 3... Brazing material, 7... Resin sealing body, 11... Die pad, lla... Mountain part Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] ダイパッド上に半導体チップを固着し、樹脂封止体で囲
い封止した半導体装置において、上記ダイパッドを複数
の山部をもつ波形に形成し、上記半導体チップを長手方
向を上記波形の方向にして各山部上にろう付け固着した
ことを特徴とする半導体装置。In a semiconductor device in which a semiconductor chip is fixed on a die pad and surrounded and sealed with a resin sealing body, the die pad is formed into a waveform having a plurality of peaks, and the semiconductor chip is arranged with its longitudinal direction in the direction of the waveform. A semiconductor device characterized by being fixed by brazing on the peak.
JP59267946A 1984-12-17 1984-12-17 Semiconductor device Granted JPS61144046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59267946A JPS61144046A (en) 1984-12-17 1984-12-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59267946A JPS61144046A (en) 1984-12-17 1984-12-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61144046A true JPS61144046A (en) 1986-07-01
JPH0141265B2 JPH0141265B2 (en) 1989-09-04

Family

ID=17451797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59267946A Granted JPS61144046A (en) 1984-12-17 1984-12-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61144046A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125458U (en) * 1991-05-07 1992-11-16 山口日本電気株式会社 Lead frame
EP0715353A3 (en) * 1994-11-29 1996-10-16 Shinko Electric Ind Co Board for a semiconductor chip
EP0771029A3 (en) * 1995-10-24 1997-07-30 Oki Electric Ind Co Ltd Semiconductor device having an improved structure for preventing cracks, and method of manufacturing the same
JP2007008569A (en) * 2005-07-04 2007-01-18 Japan Crown Cork Co Ltd Spout equipped with unsealing preventing function in circulation

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125458U (en) * 1991-05-07 1992-11-16 山口日本電気株式会社 Lead frame
EP0715353A3 (en) * 1994-11-29 1996-10-16 Shinko Electric Ind Co Board for a semiconductor chip
US5744224A (en) * 1994-11-29 1998-04-28 Shinko Electric Industries Co., Ltd. Board for mounting semiconductor chip
EP0771029A3 (en) * 1995-10-24 1997-07-30 Oki Electric Ind Co Ltd Semiconductor device having an improved structure for preventing cracks, and method of manufacturing the same
US5864174A (en) * 1995-10-24 1999-01-26 Oki Electric Industry Co., Ltd. Semiconductor device having a die pad structure for preventing cracks in a molding resin
US6177725B1 (en) 1995-10-24 2001-01-23 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
US6459145B1 (en) * 1995-10-24 2002-10-01 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor
US6569755B2 (en) 1995-10-24 2003-05-27 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same
JP2007008569A (en) * 2005-07-04 2007-01-18 Japan Crown Cork Co Ltd Spout equipped with unsealing preventing function in circulation

Also Published As

Publication number Publication date
JPH0141265B2 (en) 1989-09-04

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