JP3825197B2 - Semiconductor device - Google Patents

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JP3825197B2
JP3825197B2 JP08741799A JP8741799A JP3825197B2 JP 3825197 B2 JP3825197 B2 JP 3825197B2 JP 08741799 A JP08741799 A JP 08741799A JP 8741799 A JP8741799 A JP 8741799A JP 3825197 B2 JP3825197 B2 JP 3825197B2
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resin
semiconductor device
semiconductor chip
resin package
internal
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JP2000286367A (en
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和孝 柴田
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【発明の属する技術分野】
本願発明は、半導体チップと内部リードとがワイヤを介して接続され、これらが樹脂パッケージ内に封入された形態の半導体装置に関する。
【０００２】
【従来の技術】
従来の半導体装置の一例として、図１０に示した構造のものがある。この種の半導体装置１Ａは、金属板を打ち抜きあるいはエッチング処理するなどして得られる、いわゆるリードフレームから製造されたものである。すなわち、ダイパッド２上に実装された半導体チップ３と、樹脂パッケージ６Ａ内に形成された複数の内部リード５０とがワイヤ４を介して導通接続され、樹脂パッケージ６Ａの外部においては、各内部リード５０に一体的に連続して外部リード（外部接続用端子）５１が複数設けられた構成とされている。
【０００３】
このような構成の半導体装置１は、通常、回路基板などに実装して使用されるが、その実装方法には、ハンダリフローの手法が一般的に採用される。この方法では、外部リード５１にクリームハンダを予め塗布しておき、半導体装置１を回路基板などにおける所定の部位に位置決め載置した状態で、リフロー炉に搬入してクリームハンダを再溶融し、これを固化させることによって半導体装置１が回路基板などに実装される。
【０００４】
【発明が解決しようとする課題】
ハンダリフローの手法では、回路基板などとともにリフロー炉内に半導体装置１が搬入されるが、このときに半導体チップ３、各内部リード５０および樹脂パッケージ６Ａが膨張し、これらがハンダを固化させる際に収縮する。ところが、内部リード５０（リードフレーム２Ａ）はニッケルなどの金属によって、半導体チップ３は主としてシリコンなどによって形成されており、また樹脂パッケージ６Ａはエポキシ樹脂などによって形成されているため、加熱時においては、内部リード５０や半導体チップ３に比べて熱膨張率の高い樹脂パッケージ６Ａのほうがより膨張量が大きい。したがって、各内部リード５０と樹脂パッケージ６Ａとの間の界面、ひいては各内部リード５０と樹脂パッケージ６Ａとの接続部分に応力が集中しやすく、また半導体チップ３とワイヤ４との接続部分においても応力が集中しやすい。さらに、半導体装置１を回路基板などに実装して駆動させた場合には、半導体装置１自体の温度が１００℃程度にまで上昇することがあり、このときにも同様な理由からワイヤ４と各内部リード５０や、ワイヤ４と半導体チップ３との間の接続部分に応力が集中しやすい。
【０００５】
本願発明は、上記した事情のもとで考え出されたものであって、半導体チップと、樹脂パッケージ内に形成された複数の内部リードとがワイヤを介して導通接続された形態の半導体装置において、ワイヤと内部リードや、ワイヤと半導体チップとの間の応力集中を適切に回避することをその課題としている。
【０００６】
【発明の開示】
上記の課題を解決するため、本願発明では、次の技術的手段を講じている。すなわち、本願発明により提供される半導体装置は、半導体チップと、この半導体チップとワイヤを介して導通接続された複数の内部リードと、上記半導体チップ、上記ワイヤおよび上記複数の内部リードを封入するようにして形成された樹脂パッケージと、この樹脂パッケージの外部において上記各内部リードに導通するようにして設けられた複数の外部接続用端子と、を有する半導体装置であって、複数ある上記内部リードと上記ワイヤとの接続部位のうちの少なくとも一部は、樹脂によって封止されており、上記内部リードと上記ワイヤとの接続部位を封止した樹脂は、その熱膨張率が上記内部リードよりも大きく、かつ上記樹脂パッケージよりも小さいことを特徴としている。
【０００７】
上記構成では、ワイヤと内部リードとの接続部位（以下、適宜「第１接続部位」という）が樹脂によって封止されていることから、第１接続部位が封止樹脂によって保護された恰好とされている。そして、加熱・冷却によって樹脂パッケージが膨張・収縮したとしても、樹脂パッケージから第１接続部位に対して直接的に応力が作用することはなく、封止樹脂を介して間接的に応力が作用するにすぎずない。このため、本願発明の半導体装置では、樹脂パッケージの膨張・収縮が、第１接続部位に与える影響は極めて小さい。
【０００９】
上述したように、本願発明では第１接続部位が封止樹脂によって覆われた構成であるから、樹脂パッケージの膨張・収縮は、第１接続部位に対して間接的に影響を与えるにすぎない。一方、封止樹脂の膨張・収縮したならば、その影響が第１接続部位に対して直接的に与えられることとなる。
【００１０】
ところで、本願発明では、封止樹脂の熱膨張率が、樹脂パッケージのそれよりも小さくなされているため、加熱・冷却時における封止樹脂の膨張・収縮量は、樹脂パッケージのそれよりも小さい。したがって、第１接続部位が樹脂パッケージによって直接的に覆われている場合と比較して、封止樹脂によって覆われている場合のほうが、膨張・収縮時において第１接続部位に対して直接的に与えられる影響（応力）が小さい。
【００１１】
また、本願発明では、封止樹脂の熱膨張率が内部リードよりも大きく、かつ樹脂パッケージよりも小さくなされていることから、樹脂パッケージと封止樹脂との熱膨張率の差は、樹脂パッケージと内部リードとの熱膨張率の差よりも小さい。このため、樹脂パッケージや封止樹脂の膨張・収縮の際に、樹脂パッケージと封止樹脂との間の界面に集中する応力は、樹脂パッケージと内部リードとの間の界面に集中する応力がよりも小さい。つまり、樹脂パッケージの膨張・収縮が封止樹脂に対して直接的に与える影響は、第１接続部位が樹脂パッケージによって直接的に覆われている場合と比較して小さく、樹脂パッケージがが封止樹脂を介して第１接続部位に対して間接的に与える影響はさらに小さい。
【００１２】
結局、封止樹脂が直接的に第１接続部位に与える影響と、樹脂パッケージが間接的に第１接続部位に与える影響とを総じても、従来において樹脂パッケージの膨張・収縮が第１接続部位に対して直接的に与えていた影響よりも小さい。つまり、第１接続部位の周りにおいては、封止樹脂が樹脂パッケージと内部リードとの間のバッファー的な役割を果たし、これによって第１接続部位に作用する応力が緩和される。
【００１３】
好ましい実施の形態においては、半導体チップ上には、内部リードの数に対応し、ワイヤとの接続部位（以下、適宜「第２接続部位」という）が複数設けられており、これらの第２接続部位のうちの少なくとも一部は、樹脂によって封止されており、半導体チップとワイヤとの接続部位を封止する樹脂は、その熱膨張率が半導体チップよりも大きく、かつ樹脂パッケージよりも小さい。
【００１５】
このような構成においては、先に説明した第１接続部位と同様な理由によって第２接続部位が保護され、これに作用する応力が緩和されている。
【００１６】
好ましい実施の形態においては、各第１接続部位は、隣り合う第１接続部位どうしを繋ぐようにして一連に樹脂封止されている。
【００１７】
隣り合う第１接続部位どうしを一連に樹脂封止すれば、各内部リードの位置が封止樹脂によって固定された恰好となり、加熱・冷却時において隣り合う内部リードどうしの間が広狭することが回避される。このような構成を採用することによっても、第１接続部位に作用する応力が緩和される。
【００１８】
なお、各内部リードやこれに導通する外部接続用端子の形態は種々に変更可能である。たとえば、各内部リードや外部接続用端子を、金属板を加工することによって得られるリードフレームを用いて一体的に形成してもよいし、各内部リードを、絶縁基板の上面において、導体によってパターン形成してもよく、この場合、各外部接続用端子を、絶縁基板の下面側において、ハンダによってボール状に形成してもよい。
【００１９】
本願発明のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。
【００２０】
【発明の実施の形態】
以下、本願発明の好ましい実施の形態を、図面を参照して具体的に説明する。図１は、本願発明に係る半導体装置の一例を表す全体斜視図、図２は、図１のII−II線に沿う断面図、図３は、図１および図２に示した半導体装置の要部を拡大した平面図であって、当該要部の一部を透視した平面図である。
【００２１】
本実施形態の半導体装置１は、ダイパッド２上に半導体チップ３が実装され、この半導体チップ３と複数のリード５との間がワイヤ４を介して導通接続されている。そして、ダイパッド２、半導体チップ３、ワイヤ４などが樹脂パッケージ６によって封止されている。
【００２２】
リード５は、樹脂パッケージ６内に封入された内部リード５０と、この内部リード５０に連続するとともに樹脂パッケージ６の外部に設けられた外部リード５０とを有している。外部リード５０は、クランク状に折り曲げられており、その先端部が樹脂パッケージ６の底面と同一高さ位置において水平に延びるようになされている。すなわち、上記構成の半導体装置１では、水平状とされた部分において回路基板と接続され、実装されるようになされている。
【００２３】
そして、本実施形態においては、ワイヤ４と内部リード５０との間の接続部位が樹脂によって封止されて第１封止樹脂部７ａが形成されており、ワイヤ４と半導体チップ３との間の接続部位も樹脂によって封止されて第２封止樹脂部７ｂが形成されている。これら第１および第２封止樹脂部７ａ，７ｂは、たとえば樹脂パッケージ６よりも熱膨張率が小さく、内部リード５０よりも熱膨張率の大きな樹脂によって形成される。
【００２４】
以上のような構成とされた半導体装置１では、ワイヤ４と内部リード５０との接続部位（第１接続部位）が第１封止樹脂部によって覆われていることから、加熱・冷却によって樹脂パッケージ６が膨張・収縮したとしても、樹脂パッケージ６から第１接続部位に対して直接的に応力が作用することはなく、第１封止樹脂部７ａを介して間接的に応力が作用するにすぎずない。一方、第１封止樹脂部７ａが膨張・収縮したならば、その影響が第１接続部位に対して直接的に与えられることとなるが、第１封止樹脂部７ａの熱膨張率が、樹脂パッケージ６のそれよりも小さくされていれば、加熱・冷却時における第１封止樹脂７ａの膨張・収縮量は、樹脂パッケージ６のそれよりも小さい。したがって、第１接続部位が樹脂パッケージ６によって直接的に覆われている場合と比較して、第１封止樹脂部７ａによって覆われている場合のほうが、膨張・収縮時において第１接続部位に対して直接的に与えられる影響（応力）が小さい。
【００２５】
また、第１封止樹脂部７ａの熱膨張率が内部リード５０よりも大きく、かつ樹脂パッケージ６よりも小さくなされていれば、樹脂パッケージ６と第１封止樹脂部７ａとの熱膨張率の差は、樹脂パッケージ６と内部リード５０との熱膨張率の差よりも小さい。このため、樹脂パッケージ６や第１封止樹脂部７ａの膨張・収縮の際に、樹脂パッケージ６と第１封止樹脂部７ａとの間の界面に集中する応力は、樹脂パッケージ６と内部リード５０との間の界面に集中する応力がよりも小さい。つまり、樹脂パッケージ６の膨張・収縮が第１封止樹脂部７ａに対して直接的に与える影響は第１接続部位が樹脂パッケージ６によって直接的に覆われている場合と比較して小さく、樹脂パッケージ６が第１封止樹脂部７ａを介して第１接続部位に対して間接的に与える影響はさらに小さい。
【００２６】
結局、樹脂パッケージ６が間接的に第１接続部位に与える影響と、第１封止樹脂部７ａが直接的に第１接続部位に与える影響とを総じても、従来において樹脂パッケージの膨張・収縮が第１接続部位に対して直接的に与えていた影響よりも小さい。つまり、第１接続部位の周りにおいては、第１封止樹脂部７ａが樹脂パッケージ６と内部リード５０との間のバッファー的な役割を果たし、これによって第１接続部位に作用する応力が緩和される。
【００２７】
もちろん、第２封止樹脂部７ｂも、第１封止樹脂部７ａと同様な役割を果たすため、ワイヤ４と半導体チップ３との間の接続部位に作用する応力は格段に緩和される。
【００２８】
次に、本願発明に係る半導体装置１の製造方法を、図４ないし図８を参照して説明する。なお、上記半導体装置１の製造に使用されるリードフレームについて、図４を参照して先に説明する。
【００２９】
図４に示したように、リードフレーム２Ａは、長手方向に延びる一対のサイドメンバ２０，２０の間が、幅方向に延びるようにして一定間隔毎に設けられた複数のクロスメンバ２１によって掛け渡されている。各サイドメンバ２０および隣合うクロスメンバ２１，２１によって囲まれる領域２Ｂ内には、後において半導体装置１の構成要素となるべきダイパッド２、内部リード５０および外部リード５１が形成されている。また、上記領域２Ｂ内には、４つのダムバー２２を四辺とする矩形領域２Ｃが規定されており、この矩形領域２Ｃ内にダイパッド２の四隅部がサポートリード２３を介して支持されている。各内部リード５０は、各ダムバー２２からダイパッド２側に向けて先端部が延びるようにして形成されており、各外部リード５１は、各内部リード５０に連続して矩形領域２Ｃの外方側に形成されている。
【００３０】
上記のような形態とされたリードフレーム２Ａを用いる場合には、まずダイパッド２上に半導体チップ３が実装される。具体的には、まずシリンジなどから粘液状とされた接着剤を吐出させてこれをダイパッド２上に塗布し、この接着剤上に半導体チップ３を載置した後に、接着剤を硬化させることによって半導体チップ３が実装される。なお、接着剤としては、エポキシ樹脂などの熱硬化性樹脂を含むものが好適に採用される。もちろん、接着剤としては、シート状された固体接着剤を使用してもよいし、また常温硬化性の接着剤を用いてもよい。また、半導体チップ３は、たとえばＩＣやＬＳＩなどのベアチップであり、半導体装置１の用途に応じて適宜選択される。
【００３１】
次いで、半導体チップ３の上面に形成された各端子部（図示略）と、それぞれの端子部に対応する各内部リード５０との間がワイヤ４によって結線され、図５に示したような状態とされる。この工程は、半導体チップ３の端子部について行われるファーストボンディング工程と、内部リード５０について行われるセカンドボンディング工程とからなるが、既存のワイヤボンディング装置を用いた公知の方法によって行なわれる。
【００３２】
さらに、図６に示したように、ワイヤ４と内部リード５０との接続部位、およびワイヤ４と半導体チップ３の端子部との接続部位のそれぞれを、樹脂によって個別に封止して第１および第２封止樹脂部７ａ，７ｂを形成する。この工程は、たとえばダイパッド２上に接着剤を塗布する場合と同様に、シリンジなどから粘液状とされた樹脂を吐出させるなどして行なわれる。なお、各封止樹脂部７ａ，７ｂを形成する樹脂は、樹脂パッケージ６を構成する樹脂よりも熱膨張率が小さく、内部リード５０よりも熱膨張率の大きなものが好適に使用される。この場合、樹脂パッケージ６と各封止樹脂部７ａ，７ｂとを全く性質の異なる樹脂によって形成してもよく、また同種類の樹脂を用いるとともにその樹脂内に混入されるフィラの量を調整することによって樹脂パッケージ６と封止樹脂部７ａ，７ｂとで熱膨張率に差を設けてもよい。
【００３３】
なお、図６に示したように、ワイヤ４と内部リード５０との接続部位を個別に樹脂封止するのではなく、図７に示したように、隣接する幾つかの接続部位を、一連に樹脂によって封止して封止樹脂部７Ａを形成してもよく、また、ワイヤ４と半導体チップ３の端子部との接続部位についても、幾つかの接続部位を一連に樹脂によって封止して封止樹脂部７Ｂを形成してもよい。
【００３４】
次に、ダイパッド２、半導体チップ３、ワイヤ４および内部リード５０が樹脂パッケージ６によって封止される。この工程は、図８に示したように、たとえば型締め状態においてキャビティ空間８０を形成する上下の金型８Ａ，８Ｂを用いたトランスファーモールド法などが採用される。この方法では、キャビティ空間８０内を粘液状化された樹脂が流動し、この流動樹脂によって各内部リード５０に応力が作用するが、本実施形態ではワイヤ４の接続部位が樹脂封止されていることから、このような応力に対しても対応することができる。
【００３５】
そして、ダムバーカットやリードカット工程、リードフォーミング工程、標印工程などを経て図１ないし図３に示したような半導体装置１が得られる。
【００３６】
もちろん、本願発明は、リードフレームから製造された半導体装置１ばかりでなく、図９に示したように、内部リード５０ａがパターン形成された絶縁基板２ａ上に半導体チップ３が実装され、この半導体チップ３と各内部リード５０ａとがワイヤ４を介して導通接続されるとともに、ハンダなどによってボール状の外部端子５１ａが形成された形態の半導体装置１０についても適用可能である。
【図面の簡単な説明】
【図１】本願発明に係る半導体装置の一例を表す全体斜視図である。
【図２】図１のII−II線に沿う断面図である。
【図３】図１および図２に示した半導体装置の要部を拡大した平面図であって、当該要部の一部を透視した平面図である。
【図４】図１および図２に示した半導体装置の製造に使用されるリードフレームの平面図である。
【図５】図４に示したリードフレームに、ダイボンディングおよびワイヤボンディングをした状態を表す平面図である。
【図６】ワイヤとリードフレームの内部リードとの接続部分、およびワイヤと半導体チップとの接続部分を樹脂封止した状態を表す要部拡大図である。
【図７】図６とは異なる樹脂封止形態を表す要部拡大図である。
【図８】樹脂パッケージング工程を説明するための断面図である。
【図９】本願発明の他の実施形態に係る半導体装置を表す全体斜視図である。
【図１０】従来の半導体装置の一例を表す断面図である。
【符号の説明】
１ 半導体装置
３ 半導体チップ
４ ワイヤ
６ 樹脂パッケージ
７ａ 第１封止樹脂部
７ｂ 第２封止樹脂部
７Ａ，７Ｂ 封止樹脂部（変形例の）
５０ 内部リード
５１ 外部リード（外部接続用端子としての）
２ａ 絶縁基板（他の実施形態の）
５０ａ 内部リード（他の実施形態の）
５１ａ 外部接続用端子（他の実施形態の）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor chip and an internal lead are connected via a wire, and these are enclosed in a resin package.
[0002]
[Prior art]
As an example of a conventional semiconductor device, there is a structure shown in FIG. This type of semiconductor device 1A is manufactured from a so-called lead frame obtained by stamping or etching a metal plate. That is, the semiconductor chip 3 mounted on the die pad 2 and a plurality of internal leads 50 formed in the resin package 6A are conductively connected via the wires 4, and each internal lead 50 is provided outside the resin package 6A. A plurality of external leads (external connection terminals) 51 are provided integrally and continuously.
[0003]
The semiconductor device 1 having such a configuration is normally mounted and used on a circuit board or the like, and a solder reflow technique is generally adopted as the mounting method. In this method, cream solder is applied in advance to the external leads 51, and the semiconductor device 1 is positioned and placed on a predetermined part of a circuit board or the like, and then loaded into a reflow furnace to remelt the cream solder. By solidifying the semiconductor device 1, the semiconductor device 1 is mounted on a circuit board or the like.
[0004]
[Problems to be solved by the invention]
In the solder reflow technique, the semiconductor device 1 is carried into a reflow furnace together with a circuit board or the like. At this time, the semiconductor chip 3, each internal lead 50, and the resin package 6A expand, and when these solidify the solder, Shrink. However, the internal lead 50 (lead frame 2A) is made of metal such as nickel, the semiconductor chip 3 is mainly made of silicon, and the resin package 6A is made of epoxy resin or the like. The resin package 6A having a higher thermal expansion coefficient than the internal lead 50 and the semiconductor chip 3 has a larger expansion amount. Therefore, stress tends to concentrate on the interface between each internal lead 50 and the resin package 6A, and hence on the connection portion between each internal lead 50 and the resin package 6A, and also on the connection portion between the semiconductor chip 3 and the wire 4. Is easy to concentrate. Furthermore, when the semiconductor device 1 is mounted and driven on a circuit board or the like, the temperature of the semiconductor device 1 itself may rise to about 100 ° C. At this time, the wire 4 and each Stress tends to concentrate on the internal lead 50 and the connecting portion between the wire 4 and the semiconductor chip 3.
[0005]
The present invention has been conceived under the circumstances described above, and is a semiconductor device in which a semiconductor chip and a plurality of internal leads formed in a resin package are conductively connected via wires. The problem is to appropriately avoid stress concentration between the wire and the internal lead or between the wire and the semiconductor chip.
[0006]
DISCLOSURE OF THE INVENTION
In order to solve the above problems, the present invention takes the following technical means. That is, a semiconductor device provided by the present invention encloses a semiconductor chip, a plurality of internal leads electrically connected to the semiconductor chip via wires, and the semiconductor chip, the wires, and the plurality of internal leads. And a plurality of external connection terminals provided so as to be electrically connected to the internal leads outside the resin package, and a plurality of the internal leads At least a part of the connection portion with the wire is sealed with resin, and the resin that seals the connection portion between the internal lead and the wire has a coefficient of thermal expansion larger than that of the internal lead. And smaller than the resin package .
[0007]
In the above configuration, since the connection part (hereinafter referred to as “first connection part” as appropriate) between the wire and the internal lead is sealed with resin, the first connection part is preferably protected with the sealing resin. ing. And even if the resin package expands / shrinks due to heating / cooling, stress does not act directly on the first connection portion from the resin package, but stress acts indirectly via the sealing resin. It's nothing more than For this reason, in the semiconductor device of the present invention, the influence of the expansion / contraction of the resin package on the first connection site is extremely small.
[0009]
As described above, in the present invention, since the first connection part is covered with the sealing resin, the expansion / contraction of the resin package only indirectly affects the first connection part. On the other hand, if the sealing resin expands and contracts, the influence is directly given to the first connection site.
[0010]
By the way, in this invention, since the thermal expansion coefficient of sealing resin is made smaller than that of the resin package, the expansion / contraction amount of the sealing resin at the time of heating and cooling is smaller than that of the resin package. Therefore, compared with the case where the first connection part is directly covered with the resin package, the case where the first connection part is covered with the sealing resin is more directly applied to the first connection part during expansion / contraction. The effect (stress) is small.
[0011]
In the present invention, since the thermal expansion coefficient of the sealing resin is larger than that of the internal lead and smaller than that of the resin package, the difference in thermal expansion coefficient between the resin package and the sealing resin is different from that of the resin package. It is smaller than the difference in coefficient of thermal expansion with the internal lead. For this reason, when the resin package or sealing resin expands or contracts, the stress concentrated on the interface between the resin package and the sealing resin is more stress concentrated on the interface between the resin package and the internal lead. Is also small. In other words, the effect of the expansion and contraction of the resin package directly on the sealing resin is small compared to the case where the first connection part is directly covered by the resin package, and the resin package is sealed. The influence indirectly exerted on the first connection site via the resin is even smaller.
[0012]
As a result, even if the influence of the sealing resin directly on the first connection part and the influence of the resin package indirectly on the first connection part are combined, the expansion / contraction of the resin package in the conventional case is the first connection part. It is less than the direct impact on it. That is, around the first connection site, the sealing resin plays a role of a buffer between the resin package and the internal lead, thereby relieving the stress acting on the first connection site.
[0013]
In a preferred embodiment, a plurality of connection portions (hereinafter referred to as “second connection portions” as appropriate) corresponding to the number of internal leads are provided on the semiconductor chip, and these second connections are provided. At least a part of the part is sealed with resin, and the resin that seals the connection part between the semiconductor chip and the wire has a coefficient of thermal expansion larger than that of the semiconductor chip and smaller than that of the resin package .
[0015]
In such a configuration, the second connection portion is protected for the same reason as the first connection portion described above, and the stress acting on the second connection portion is relaxed.
[0016]
In a preferred embodiment, each first connection part is sealed with a series of resins so as to connect adjacent first connection parts.
[0017]
If the adjacent first connection parts are sealed with a series of resin, the position of each internal lead is fixed by the sealing resin, and it is avoided that the adjacent internal leads are widened between heating and cooling. Is done. Also by adopting such a configuration, the stress acting on the first connection site is relieved.
[0018]
The form of each internal lead and the external connection terminal connected to the internal lead can be variously changed. For example, each internal lead or external connection terminal may be integrally formed using a lead frame obtained by processing a metal plate, or each internal lead may be patterned with a conductor on the upper surface of the insulating substrate. In this case, each external connection terminal may be formed into a ball shape by solder on the lower surface side of the insulating substrate.
[0019]
Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings. 1 is an overall perspective view illustrating an example of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and FIG. 3 is a schematic diagram of the semiconductor device shown in FIGS. It is the top view which expanded the part, Comprising: It is the top view which saw through a part of the said principal part.
[0021]
In the semiconductor device 1 of this embodiment, a semiconductor chip 3 is mounted on a die pad 2, and the semiconductor chip 3 and a plurality of leads 5 are conductively connected via wires 4. The die pad 2, the semiconductor chip 3, the wire 4, etc. are sealed with a resin package 6.
[0022]
The lead 5 has an internal lead 50 sealed in the resin package 6 and an external lead 50 that is continuous with the internal lead 50 and provided outside the resin package 6. The external lead 50 is bent in a crank shape, and its tip end portion extends horizontally at the same height as the bottom surface of the resin package 6. That is, in the semiconductor device 1 having the above configuration, the circuit board is connected and mounted at the horizontal portion.
[0023]
In this embodiment, the connection portion between the wire 4 and the internal lead 50 is sealed with resin to form the first sealing resin portion 7a, and between the wire 4 and the semiconductor chip 3 is formed. The connection site is also sealed with resin to form the second sealing resin portion 7b. The first and second sealing resin portions 7 a and 7 b are formed of a resin having a smaller coefficient of thermal expansion than the resin package 6 and a larger coefficient of thermal expansion than the internal lead 50, for example.
[0024]
In the semiconductor device 1 configured as described above, since the connection portion (first connection portion) between the wire 4 and the internal lead 50 is covered with the first sealing resin portion, the resin package is heated and cooled. Even if 6 expands and contracts, stress does not act directly on the first connection portion from the resin package 6, but only stress acts indirectly via the first sealing resin portion 7 a. No. On the other hand, if the first sealing resin portion 7a expands / contracts, the influence is directly given to the first connection site, but the thermal expansion coefficient of the first sealing resin portion 7a is: If it is smaller than that of the resin package 6, the amount of expansion / contraction of the first sealing resin 7 a during heating / cooling is smaller than that of the resin package 6. Therefore, compared to the case where the first connection portion is directly covered by the resin package 6, the case where the first connection portion is covered by the first sealing resin portion 7a is more likely to be the first connection portion during expansion / contraction. On the other hand, the influence (stress) directly exerted is small.
[0025]
Further, if the thermal expansion coefficient of the first sealing resin portion 7a is larger than that of the internal lead 50 and smaller than that of the resin package 6, the thermal expansion coefficient of the resin package 6 and the first sealing resin portion 7a is reduced. The difference is smaller than the difference in coefficient of thermal expansion between the resin package 6 and the internal lead 50. For this reason, when the resin package 6 and the first sealing resin portion 7a are expanded and contracted, the stress concentrated on the interface between the resin package 6 and the first sealing resin portion 7a is caused by the resin package 6 and the internal lead. The stress concentrated at the interface with 50 is smaller. That is, the influence that the expansion / contraction of the resin package 6 directly has on the first sealing resin portion 7a is smaller than that in the case where the first connection portion is directly covered with the resin package 6, The influence of the package 6 indirectly on the first connection site via the first sealing resin portion 7a is even smaller.
[0026]
As a result, even if the influence of the resin package 6 indirectly on the first connection portion and the influence of the first sealing resin portion 7a directly on the first connection portion are combined, the expansion and contraction of the resin package in the related art is not possible. It is smaller than the influence directly given to the first connection site. That is, around the first connection part, the first sealing resin portion 7a plays a role of a buffer between the resin package 6 and the internal lead 50, thereby relieving the stress acting on the first connection part. The
[0027]
Of course, since the second sealing resin portion 7b also plays the same role as the first sealing resin portion 7a, the stress acting on the connection portion between the wire 4 and the semiconductor chip 3 is remarkably reduced.
[0028]
Next, a method for manufacturing the semiconductor device 1 according to the present invention will be described with reference to FIGS. The lead frame used for manufacturing the semiconductor device 1 will be described first with reference to FIG.
[0029]
As shown in FIG. 4, the lead frame 2A is spanned by a plurality of cross members 21 provided at regular intervals so as to extend in the width direction between the pair of side members 20, 20 extending in the longitudinal direction. Has been. In the region 2B surrounded by the side members 20 and the adjacent cross members 21 and 21, die pads 2, internal leads 50, and external leads 51 to be components of the semiconductor device 1 later are formed. Further, a rectangular area 2C having four sides of four dam bars 22 is defined in the area 2B, and the four corners of the die pad 2 are supported via support leads 23 in the rectangular area 2C. Each internal lead 50 is formed so that the tip end portion extends from each dam bar 22 toward the die pad 2 side, and each external lead 51 is continuous with each internal lead 50 on the outer side of the rectangular region 2C. Is formed.
[0030]
When using the lead frame 2 </ b> A configured as described above, the semiconductor chip 3 is first mounted on the die pad 2. Specifically, by first discharging a viscous liquid adhesive from a syringe or the like and applying it onto the die pad 2, placing the semiconductor chip 3 on the adhesive, and then curing the adhesive A semiconductor chip 3 is mounted. In addition, as an adhesive agent, what contains thermosetting resins, such as an epoxy resin, is employ | adopted suitably. Of course, as the adhesive, a sheet-like solid adhesive may be used, or a room temperature curable adhesive may be used. Further, the semiconductor chip 3 is a bare chip such as an IC or an LSI, for example, and is appropriately selected according to the application of the semiconductor device 1.
[0031]
Next, each terminal part (not shown) formed on the upper surface of the semiconductor chip 3 and each internal lead 50 corresponding to each terminal part are connected by the wire 4, and the state as shown in FIG. Is done. This process includes a first bonding process performed on the terminal portion of the semiconductor chip 3 and a second bonding process performed on the internal lead 50, and is performed by a known method using an existing wire bonding apparatus.
[0032]
Further, as shown in FIG. 6, each of the connection portion between the wire 4 and the internal lead 50 and the connection portion between the wire 4 and the terminal portion of the semiconductor chip 3 are individually sealed with resin to form the first and Second sealing resin portions 7a and 7b are formed. This step is performed, for example, by discharging a viscous liquid from a syringe or the like, as in the case of applying an adhesive onto the die pad 2. As the resin forming the sealing resin portions 7 a and 7 b, a resin having a smaller thermal expansion coefficient than that of the resin constituting the resin package 6 and a larger thermal expansion coefficient than that of the internal lead 50 is preferably used. In this case, the resin package 6 and the sealing resin portions 7a and 7b may be formed of resins having completely different properties, and the same kind of resin is used and the amount of filler mixed in the resin is adjusted. Accordingly, the resin package 6 and the sealing resin portions 7a and 7b may have a difference in thermal expansion coefficient.
[0033]
In addition, as shown in FIG. 6, instead of individually sealing the connecting portions between the wires 4 and the internal leads 50, as shown in FIG. The sealing resin portion 7 </ b> A may be formed by sealing with resin. Also, with respect to the connection portion between the wire 4 and the terminal portion of the semiconductor chip 3, several connection portions are sequentially sealed with resin. The sealing resin portion 7B may be formed.
[0034]
Next, the die pad 2, the semiconductor chip 3, the wires 4 and the internal leads 50 are sealed with the resin package 6. As shown in FIG. 8, this process employs, for example, a transfer molding method using upper and lower molds 8A and 8B that form the cavity space 80 in a mold-clamped state. In this method, the viscous resin flows in the cavity space 80, and stress acts on each internal lead 50 by the fluid resin. However, in this embodiment, the connection portion of the wire 4 is resin-sealed. Therefore, it is possible to cope with such stress.
[0035]
Then, the semiconductor device 1 as shown in FIGS. 1 to 3 is obtained through a dam bar cut, a lead cut process, a lead forming process, a marking process, and the like.
[0036]
Of course, in the present invention, not only the semiconductor device 1 manufactured from the lead frame but also the semiconductor chip 3 is mounted on the insulating substrate 2a on which the internal leads 50a are patterned as shown in FIG. 3 and each internal lead 50a are electrically connected via the wire 4, and the present invention is also applicable to the semiconductor device 10 in which a ball-like external terminal 51a is formed by solder or the like.
[Brief description of the drawings]
FIG. 1 is an overall perspective view illustrating an example of a semiconductor device according to the present invention.
2 is a cross-sectional view taken along line II-II in FIG.
3 is an enlarged plan view of a main part of the semiconductor device shown in FIGS. 1 and 2, and is a plan view in which a part of the main part is seen through. FIG.
4 is a plan view of a lead frame used for manufacturing the semiconductor device shown in FIGS. 1 and 2. FIG.
5 is a plan view showing a state in which die bonding and wire bonding are performed on the lead frame shown in FIG. 4; FIG.
FIG. 6 is an enlarged view of a main part showing a state where a connection portion between a wire and an internal lead of a lead frame and a connection portion between the wire and a semiconductor chip are sealed with resin.
7 is an enlarged view of a main part showing a resin sealing form different from FIG. 6. FIG.
FIG. 8 is a cross-sectional view for explaining a resin packaging process.
FIG. 9 is an overall perspective view showing a semiconductor device according to another embodiment of the present invention.
FIG. 10 is a cross-sectional view illustrating an example of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Semiconductor chip 4 Wire 6 Resin package 7a 1st sealing resin part 7b 2nd sealing resin part 7A, 7B Sealing resin part (in a modification)
50 Internal lead 51 External lead (as an external connection terminal)
2a Insulating substrate (of other embodiments)
50a Internal lead (of other embodiments)
51a External connection terminal (in other embodiments)

Claims (6)

半導体チップと、この半導体チップとワイヤを介して導通接続された複数の内部リードと、上記半導体チップ、上記ワイヤおよび上記複数の内部リードを封入するようにして形成された樹脂パッケージと、この樹脂パッケージの外部において上記各内部リードに導通するようにして設けられた複数の外部接続用端子と、を有する半導体装置であって、
複数ある上記内部リードと上記ワイヤとの接続部位のうちの少なくとも一部は、樹脂によって封止されており、
上記内部リードと上記ワイヤとの接続部位を封止した樹脂は、その熱膨張率が上記内部リードよりも大きく、かつ上記樹脂パッケージよりも小さいことを特徴とする、半導体装置。A semiconductor chip, a plurality of internal leads electrically connected to the semiconductor chip via wires, a resin package formed so as to enclose the semiconductor chip, the wires and the plurality of internal leads, and the resin package A plurality of external connection terminals provided so as to be electrically connected to each of the internal leads outside of the semiconductor device,
At least a part of the connection portion between the plurality of internal leads and the wire is sealed with resin ,
A semiconductor device characterized in that a resin sealing a connection portion between the internal lead and the wire has a coefficient of thermal expansion larger than that of the internal lead and smaller than that of the resin package . 上記半導体チップ上には、上記複数の内部リードに対応して上記ワイヤとの接続部位が複数設けられており、これらの接続部位のうちの少なくとも一部は、樹脂によって封止されており、
上記半導体チップと上記ワイヤとの接続部位を封止する樹脂は、その熱膨張率が上記半導体チップよりも大きく、かつ上記樹脂パッケージよりも小さい、請求項１に記載の半導体装置。On the semiconductor chip, a plurality of connection portions with the wires are provided corresponding to the plurality of internal leads, and at least a part of these connection portions is sealed with a resin ,
The semiconductor device according to claim 1 , wherein a resin that seals a connection portion between the semiconductor chip and the wire has a coefficient of thermal expansion larger than that of the semiconductor chip and smaller than that of the resin package . 上記内部リードと上記ワイヤとの接続部位は、隣り合う接続部位どうしを繋ぐようにして一連に樹脂封止されている、請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the connection portion between the internal lead and the wire is resin-sealed in series so as to connect adjacent connection portions. 上記各内部リードおよびこれに導通する外部接続用端子は、金属板を加工することによって得られるリードフレームを用いて一体的に形成されている、請求項１ないし３のいずれかに記載の半導体装置。Each internal lead and the external connection terminals electrically connected to this, are integrally formed using a lead frame obtained by processing a metal plate, a semiconductor device according to any one of claims 1 to 3 . 上記各内部リードは、絶縁基板の上面において、導体によってパターン形成されたものである、請求項１ないし３のいずれかに記載の半導体装置。Each inner lead, the upper surface of the insulating substrate, in which patterned by a conductor, semiconductor device according to any one of claims 1 to 3. 上記各外部接続用端子は、上記絶縁基板の下面側において、ハンダによってボール状に形成されたものである、請求項５に記載の半導体装置。6. The semiconductor device according to claim 5 , wherein each of the external connection terminals is formed in a ball shape by solder on the lower surface side of the insulating substrate.
JP08741799A 1999-03-30 1999-03-30 Semiconductor device Expired - Fee Related JP3825197B2 (en)

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