JP2589118B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2589118B2 JP2589118B2 JP63007405A JP740588A JP2589118B2 JP 2589118 B2 JP2589118 B2 JP 2589118B2 JP 63007405 A JP63007405 A JP 63007405A JP 740588 A JP740588 A JP 740588A JP 2589118 B2 JP2589118 B2 JP 2589118B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- junction
- semiconductor device
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は樹脂封止型半導体装置にかかり、特に比較
的大型の半導体チップを用い半導体チップ組立体をジャ
ンクションコートレジンで被覆したものに樹脂モールド
を施した樹脂封止型半導体装置に適用される。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a resin-encapsulated semiconductor device, and particularly, covers a semiconductor chip assembly with a junction coat resin using a relatively large semiconductor chip. The present invention is applied to a resin-encapsulated semiconductor device in which a resin mold is applied to a semiconductor device.
（従来の技術） 従来、一例の樹脂封止型半導体装置を第３図に示す。
第３図ａは上方から透視して視た内部構造を示す断面
図、第３図ｂは第３図ａのAA線に沿う断面図である。図
に示すように、リードフレーム101におけるチップベッ
ド101aはこれに半導体チツプ102をはんだ（Sn−Pb−Ag
系）で取付け、この半導体チップの電極はアルミニウム
などの金属細線103（500μ径）でリード101bにワイヤボ
ンディングが施されて半導体チップ組立体104が形成さ
れている。また、前記半導体チップ組立体の半導体チッ
プ102と電極線部（ワイヤボンディング）を被覆するよ
うにチップベッド101aの主面上にゲル状のジャンクショ
ンレジン体105が盛り付けられている。そして、熱硬化
性のモールド樹脂でモールドを施し樹脂封止体106が形
成され、樹脂封止型半導体装置が得られている。なお、
図中の116はモールド樹脂が導入されるゲート部の樹脂
残部である。(Prior Art) Conventionally, an example of a resin-sealed semiconductor device is shown in FIG.
FIG. 3A is a cross-sectional view showing the internal structure viewed from above, and FIG. 3B is a cross-sectional view along the line AA in FIG. 3A. As shown in the figure, a chip bed 101a of a lead frame 101 is soldered with a semiconductor chip 102 (Sn-Pb-Ag).
The electrode of this semiconductor chip is wire-bonded to the lead 101b with a thin metal wire 103 (500 μ diameter) such as aluminum to form a semiconductor chip assembly 104 . A gel-like junction resin body 105 is provided on the main surface of the chip bed 101a so as to cover the semiconductor chip 102 and the electrode wires (wire bonding) of the semiconductor chip assembly. Then, molding is performed with a thermosetting molding resin to form a resin sealing body 106, and a resin sealing semiconductor device is obtained. In addition,
Reference numeral 116 in the figure denotes a remaining resin portion of the gate portion into which the mold resin is introduced.
（発明が解決しようとする課題） 叙上と従来の構造によると、ジャンクションレジンを
チップベッド上の全体に行きわたるように多い目に施し
ても、なお、樹脂モールド時にモールド樹脂に押されて
第３図ｂに破線で囲む部分のジャンクションレジン体11
5が流失、変形し、所望の形状のジャンクションレジン
体が得られない。このため、半導体ペレットの特に稜線
部や角部のジャンクションレジン体が薄くなり、半導体
ペレットにクラックが発生するという重大な問題点があ
る。(Problems to be Solved by the Invention) According to the above description and the conventional structure, even if the junction resin is applied to a large number of eyes so as to spread over the entirety of the chip bed, it is still pressed by the molding resin during the resin molding. 3 A portion of the junction resin body 11 surrounded by a broken line in FIG.
5 is lost and deformed, and a junction resin body having a desired shape cannot be obtained. For this reason, there is a serious problem that the junction resin body of the semiconductor pellet, particularly at the ridge and corner portions, becomes thin, and cracks occur in the semiconductor pellet.
この発明は上述の問題点に鑑み、樹脂封止型半導体装
置の改良構造を提供するものである。The present invention has been made in view of the above problems, and provides an improved structure of a resin-sealed semiconductor device.
（課題を解決するための手段） この発明にかかる樹脂封止型半導体装置は、リードフ
レームのチップベッドに取付けられた半導体チップと、
この半導体チップの電極配線を施した半導体チップ組立
体と、この半導体チップ組立体の半導体チップと電極配
線部を被覆するジャンクションレジン体と、前記リード
レフームの半導体チップ組立体とジャンクションレジン
体を含み樹脂モールドを施し形成された樹脂封止体を具
備した樹脂封止型半導体装置において、チップベッドに
おけるそのモールド樹脂の導入ゲート側の端縁に、樹脂
封止体の封入により生ずるジャンクションレジン体の変
形を防止するために半導体チップの厚さに相当する高さ
に形成されたモールド樹脂流緩衝部を有することを特徴
とする。(Means for Solving the Problems) A resin-encapsulated semiconductor device according to the present invention includes: a semiconductor chip mounted on a chip bed of a lead frame;
A semiconductor chip assembly provided with the electrode wiring of the semiconductor chip, a junction resin body covering the semiconductor chip and the electrode wiring portion of the semiconductor chip assembly, and a resin mold including the semiconductor chip assembly and the junction resin body of the lead refume. In the resin-encapsulated semiconductor device having the resin-encapsulated body formed by applying the resin, the deformation of the junction resin body caused by encapsulation of the resin-encapsulated body at the edge of the chip bed on the introduction gate side of the molding resin is prevented. And a mold resin flow buffer formed at a height corresponding to the thickness of the semiconductor chip.
（作 用） この発明は封止用のモールド樹脂によりゲル状ジャン
クションレジン体が押し流されて所望の形状、厚さが損
ぜられ、半導体チップにクラックが生ずるのを防止でき
る。また、チップベッドに取付けできる半導体チップの
大型化がはかれる。(Operation) According to the present invention, it is possible to prevent a gel-like junction resin body from being washed away by a sealing mold resin, thereby impairing a desired shape and thickness, and preventing a semiconductor chip from being cracked. Further, the size of the semiconductor chip that can be attached to the chip bed is increased.
（実施例） 以下、この発明の実施例につき、まず第１図によって
説明する。なお、説明において従来と変わらない部分に
ついては、図面に従来と同じ符号をつけて示し説明を省
略する。Embodiment An embodiment of the present invention will be described below with reference to FIG. In the description, portions that are the same as those in the related art are denoted by the same reference numerals in the drawings, and description thereof is omitted.
この実施例の半導体チップ組立体10のリードフレーム
11は方形のチップベッド12のモールド樹脂導入側端縁辺
の部分が半導体チップ102の厚さ、一例の0.3mm相当の高
さに半導体チップ取付け主面側へ折り曲げられて、樹脂
封止体の封入により生ずるジャンクションレジン体の変
形を防止するためのモールド樹脂流緩衝部12aになって
いる。このモールド樹脂流緩衝部12aは一例としてプレ
ス加工によって形成され、その形状は第１図には連続し
た型を示すが、第２図に示すように半導体チップ組立体
20のリードフレーム21におけるチップベッド22に断続か
つ角部に設けたモールド樹脂流緩衝部22aの形状でもよ
い。この第２図に示すチップベッド22の場合、その高さ
は叙上の半導体チップの厚さ相当の0.3mm以上あればよ
いが、余り高くするとこのモールド樹脂流緩衝部の両端
から裏面へジャンクションレジンが流れてしまい次の樹
脂モールドに支障を生ずるので、0.5mm程度が適当であ
る。ジャンクションレジンは一例としてシリコーン樹脂
JCB 6105,JCR6109（いずれも商品名、トーレシリコーン
製）を用い、粘度は作業性から300〜750p.（ポイズ）が
適当である。また、ジャンクションレジンはチップベッ
ド全面に、かつモールド樹脂流緩衝部の稜線（最高部）
に至るまで裏面に流れない程度盛って半導体チップ102
を完全に埋め込むように被覆する。次に施される樹脂モ
ールドによる封止は、トランスファモールド法にて、エ
ポキシ系熱硬化樹脂を用いて達成される。Lead frame of semiconductor chip assembly 10 of this embodiment
11 is a rectangular chip bed 12 in which the edge of the molding resin introduction side edge is bent toward the semiconductor chip mounting main surface side to the thickness of the semiconductor chip 102, for example, a height equivalent to 0.3 mm, and encloses a resin sealing body. This serves as a mold resin flow buffering portion 12a for preventing the deformation of the junction resin body caused by the above. The mold resin flow buffering section 12a is formed by press working as an example, and the shape thereof is shown as a continuous mold in FIG. 1, but as shown in FIG.
The shape of the mold resin flow buffering portion 22a intermittently provided in the chip bed 22 of the 20 lead frames 21 and provided at the corners may be used. In the case of the chip bed 22 shown in FIG. 2, the height may be at least 0.3 mm corresponding to the thickness of the semiconductor chip described above. Is flowed, which causes trouble for the next resin mold. Junction resin is silicone resin as an example
JCB 6105 and JCR 6109 (both trade names, manufactured by Toray Silicone) are used, and the viscosity is suitably 300 to 750 p. (Poise) from the viewpoint of workability. In addition, the junction resin covers the entire chip bed and the ridgeline (the highest part) of the mold resin flow buffer.
Semiconductor chip 102
Is completely embedded. The encapsulation by a resin mold to be performed next is achieved by a transfer molding method using an epoxy-based thermosetting resin.
なお、半導体チップSCR,ICをはじめ、トランジスタ・
アレイのように複数個並んでいても適用される 叙上の構成にて、厚さ0.8mmの銅系の材料であるリー
ドフレームの約10mm角のチップベッド上に7mm角の半導
体チップをはんだ付けし、ゲル状ジャンクションレジ
ン、一例のJCR 6109（トーレシリコーン製）を前記チッ
プベッド上の全面およびモールド樹脂流緩衝部高さ0.5m
mの稜線まで施した場合、チップ約150個中クラックの発
生は皆無であり、流れ止めを設けない従来の場合のクラ
ック発生が0.4〜1.0％であったのに比し、顕著に向上を
みている。In addition, transistors, including semiconductor chips SCR and IC,
Applicable even when multiple arrays are arranged like an array In the above configuration, a 7mm square semiconductor chip is soldered on a chipbed of about 10mm square of a 0.8mm thick copper-based lead frame Then, a gel-like junction resin, such as JCR 6109 (made by Toray Silicone), was placed on the entire surface of the chip bed and the height of the mold resin flow buffer was 0.5 m.
When applied up to the ridge line of m, no crack was generated in about 150 chips, and the crack generation was remarkably improved compared to 0.4 to 1.0% in the conventional case without the flow stop. I have.
この発明によれば、半導体チップを被覆するようにチ
ップベッド上に盛り付けるゲル状のジャンクションレジ
ン体の形状が、次の樹脂モールドによって流され、特に
モールド樹脂が圧入されるゲート側で半導体チップの稜
線、角部等で薄くなるのが完全に防止され、これにより
半導体チップに発生するクラックが防止される。According to the present invention, the shape of the gel-like junction resin body to be laid on the chip bed so as to cover the semiconductor chip is flowed by the next resin mold, and particularly the ridge of the semiconductor chip on the gate side where the mold resin is pressed. , Corners, etc., is completely prevented, thereby preventing cracks occurring in the semiconductor chip.
次にゲル状のジャンクションレジン体の量を多く、厚
く盛りつけることができる。Next, the amount of the gel-like junction resin body is large and can be thickened.
叙上により、従来銅系リードフレーム上にはんだ付け
により取付けできる半導体チップの大きさは約6mm角が
限度でかつ、クラックの発生があったが、7mm角でもク
ラックの発生を防止できるなどの顕著な利点がある。As described above, the size of a semiconductor chip that can be mounted on a copper-based lead frame by soldering in the past was limited to about 6 mm square and cracks occurred, but cracks can be prevented even with a 7 mm square. There are significant advantages.
第１図はこの発明の一実施例の樹脂封止型半導体装置に
かゝり第１図ａは上方から透視した内部構造の断面図，
第１図ｂは第１図ａのAA線に沿う断面図、第２図はこの
発明の別の実施例にかかり第２図ａは上方から透視した
内部構造の断面図，第２図ｂは第２図ａのAA線に沿う断
面図、第３図は従来の樹脂封止型半導体装置にかかり第
３図ａは上方から透視した内部構造の断面図，第３図ｂ
は第ａ図のAA線に沿う断面図である。10 ，20……半導体チップ組立体11 ，21……リードフレーム 12,22……チップベッド 12a,22a……モールド樹脂流緩衝部 102……半導体チップ 103……金属細線 105……ジャンクションレジン体 106……樹脂封止体FIG. 1 is a cross-sectional view of an internal structure seen from above, and FIG.
1b is a cross-sectional view taken along the line AA of FIG. 1a, FIG. 2 is a cross-sectional view of an internal structure viewed from above according to another embodiment of the present invention, and FIG. FIG. 2A is a cross-sectional view taken along the line AA of FIG. 2, FIG. 3 is a cross-sectional view of the internal structure of the conventional resin-encapsulated semiconductor device seen from above, FIG.
FIG. 4 is a sectional view taken along the line AA in FIG. 10 , 20 … Semiconductor chip assemblies 11 , 21 … Lead frames 12, 22… Chip beds 12a, 22a… Mold resin flow buffer 102… Semiconductor chips 103… Thin metal wires 105… Junction resin bodies 106 …… Resin sealed body
Claims (1)
れた半導体チップと、この半導体チップの電極配線を施
した半導体チップ組立体と、この半導体チップ組立体の
半導体チップと電極配線部を被覆するジャンクションレ
ジン体と、前記リードレフームの半導体チップ組立体と
ジャンクションレジン体を含み樹脂モールドを施し形成
された樹脂封止体を具備した樹脂封止型半導体装置にお
いて、チップベッドにおけるそのモールド樹脂の導入ゲ
ート側の端縁に、樹脂封止体の封入により生ずるジャン
クションレジン体の変形を防止するために半導体チップ
の厚さに相当する高さに形成されたモールド樹脂流緩衝
部を有することを特徴とする樹脂封止型半導体装置。1. A semiconductor chip mounted on a chip bed of a lead frame, a semiconductor chip assembly provided with electrode wiring of the semiconductor chip, and a junction resin for covering the semiconductor chip and electrode wiring portion of the semiconductor chip assembly. And a resin-encapsulated semiconductor device having a resin-encapsulated body formed by applying a resin mold and including a semiconductor chip assembly of the lead-refom and a junction resin, the end of the chip bed on the introduction gate side of the molding resin. Resin sealing, characterized in that the edge has a molded resin flow buffer formed at a height corresponding to the thickness of the semiconductor chip in order to prevent deformation of the junction resin body caused by enclosing the resin sealing body. Type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63007405A JP2589118B2 (en) | 1988-01-19 | 1988-01-19 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63007405A JP2589118B2 (en) | 1988-01-19 | 1988-01-19 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01183838A JPH01183838A (en) | 1989-07-21 |
| JP2589118B2 true JP2589118B2 (en) | 1997-03-12 |
Family
ID=11664963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63007405A Expired - Fee Related JP2589118B2 (en) | 1988-01-19 | 1988-01-19 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2589118B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5362473A (en) * | 1976-11-17 | 1978-06-03 | Hitachi Ltd | Production of semiconductor device |
-
1988
- 1988-01-19 JP JP63007405A patent/JP2589118B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01183838A (en) | 1989-07-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |