JPS61142757A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a highly reliable semiconductor device, in which wiring defects do not occur in a lower wiring layer and an upper wiring layer and the miniaturized upper wiring layer is provided, by providing an insulating layer between the wiring layers having a laminated structure, wherein the lower layer is a heat resisting organic insulating layer and the upper layer is a plasma chemical vapor deposition inorganic insulating layer. CONSTITUTION:On a semiconductor substrate 1, a thermal oxide film 2, from which an impurity region is removed, is formed. A metal film (Al-Si) for a lower wiring layer is deposited on the film 2. Then etching is performed, and a first conducting metal layer 3 is formed. For example, a polyimide resin insulating material is applied on the entire surface, and a heat resisting organic insulating layer 5 is formed. A plasma excited vapor-deposition inorganic insulating layer 4 comprising a P-SiN film is formed on the layer 5. Then, the P-SiN film 4 and the polyimide film 5 are continuously etched, and a window 9 for connecting the upper and lower wirings is penetrated. Thereafter, a metal film (Al-Cu) for upper wiring layer is deposited on the surface of the inorganic insulating film 4. The window 9 is filled by the film at the same time. Selective etching is performed, and a minute second conducting metal layer 6, which is the upper wiring layer, is formed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device having a multilayer wiring structure having a V4 layer insulating film between wiring layers, and particularly relates to a semiconductor device having a multilayer wiring structure including a V4 layer insulating film between wiring layers, and in particular, in addition to flattening the wiring, it also reduces the risk of wiring defects. The present invention relates to a semiconductor device that is free of wires and can form finer wiring.

[Technical Background of the Invention] Conventionally, semiconductor devices having a multilayer wiring structure for planarizing wiring are known to include the following laminated insulating film as an interlayer insulating film.

FIG. 2 is a sectional view of a wiring structure portion of the known semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a hot melt film (Si02) formed on the surface of the semiconductor substrate 1, and 3
4 is an inorganic insulating film formed on the lower layer wiring 3 and the thermal oxide film 2; 5 is a lower layer wiring formed on the thermal oxide 1Ii2;
5A is an organic insulating film laminated on the inorganic insulating film 4.
6 is an altered layer formed on the surface layer of the organic insulating film 5, and 6 is an upper layer wiring formed on the organic insulating film 5. Note that the inorganic insulating film 4 is formed using a plasma-enhanced chemical vapor deposition method (plasma C
A plasma silicon nitride film (abbreviated as a P-8i N film) formed by a VD method (also called VD method) is commonly used, and an insulating film containing polyimide resin as a main component is commonly used as the organic insulating film 5. 6a is a pattern etched portion arranged in the upper layer.

A conventional semiconductor device as shown in Figure 2 has a laminated structure (multilayer structure) in which the lower layer is an inorganic insulating film and the upper layer is an organic insulating film.
The insulating film of this structure is provided as an interlayer insulating film, and since the surface of the insulating film of this structure can be easily flattened, it has favorable properties as an interlayer insulating film of a multilayer wiring structure.

The known semiconductor device is manufactured by the method shown in FIG.

First, as shown in FIG. 3(A), the lower layer arrangement 13 and thermal oxidation! ! An inorganic insulating film 4 is formed on 2 by plasma CVD method.
After depositing (P-8i N11l), heat treatment is performed as a pretreatment for applying an organic insulator (an insulator whose main component is polyimide resin), and the organic insulator is applied, followed by a heat curing treatment. , an organic insulating film 5 is laminated on the inorganic insulating film 4 .

Next, as shown in FIG. 3(8), a resist pattern 7 is formed on the organic insulating film 5 by a known photoetching process (PEP), and then reactive ion etching (RlE) is performed using the resist pattern 7 as a mask. ), the organic insulating film 5 and inorganic insulating film 4 on the lower wiring 3 are continuously etched to form through holes 8 in the insulating film. When this RlE is performed, a resist deteriorated layer 7A is generated on the surface of the resist pattern 7, so after forming the through hole, RIE is performed using oxygen as a working gas to remove the resist deteriorated layer 7A as shown in FIG. 3(C). put. Next, after the resist pattern 7 is peeled off using an organic solvent, a heat treatment is performed as a pretreatment for forming upper layer wiring.

Then, after performing sputtering to remove oxides from the surface of the lower layer wiring 3 to prevent connection failures between the upper and lower wires in the through hole 8, the upper layer is successively applied to the organic material aJl!5 using a sputtering method. Wiring metal 11 (AI-Cu
) is deposited. Finally, by selectively wet-etching the metal film, a pattern of upper layer wiring 6 is formed on organic insulation 15 as shown in FIG. 3(D).

In this case, since the Ar sputtering process was performed, a degraded layer 5A of organic insulator is formed on the surface of organic insulator yi59.

[Problems of Background Art] The conventional semiconductor device as described above has the following problems.

■ The lower layer wiring 3 is covered with a P-8i N film, but since P-8i NII has the property of generating high internal stress, the lower layer wiring 3 is coated with a P-8iN film as shown in Figures 4 (a) and (b). As shown, it can be seen that a wedge-shaped defect 3a is generated. When such a defective portion 3a occurs, the resistance to elect-0 migration of the wiring decreases, making it more susceptible to disconnection.

■ As seen in the above manufacturing method, since the surface of the organic insulating film 5 is subjected to Ar sputtering before the formation of the upper layer wiring, an altered layer 5A is formed on the surface of the organic insulating film, and on top of this altered layer 5A. The upper layer wiring 6 is placed on the etched portion 6a of the upper layer wiring pattern, and the organic insulating film deteriorated layer 5 is placed inside the etched portion 6a of the upper layer wiring pattern.
Since A is exposed, the following problem occurs.

(a) Since the altered layer 5A exists under the upper layer wiring 6, the surface inversion threshold m voltage of the non-element region is 10 to 20.
%, and the variation in its value (surface inversion threshold voltage) increases.

(b) Since the organic insulation wA5 is altered by the Ar sputtering, such as carbonization, unevenness occurs between the upper layer wirings 6a. Therefore, in order to prevent such leakage from occurring, it is necessary to perform RIE using oxygen to remove the altered layer 5A, but this increases the manufacturing cost due to the increase in the number of steps.

■ In order to improve the coverage of the upper layer wiring, it is necessary to deposit the upper layer wiring metal Ml (AI-Cu) at a high temperature of 380°C or higher, but when deposited at such a high temperature, rigging occurs on the surface of the organic insulating film. Because a reaction product between (AI-Cu) and the organic insulator (polyimide resin) is generated, the upper layer arrangement 1 formed by etching the metal film
The reactant is present in fl16a, causing a short circuit between the upper layer wirings and causing leakage.

Therefore, in order to prevent such leakage, it is necessary to perform dry etching such as Ar sputtering after forming the upper layer wiring to remove the reactant, but this also increases the number of steps and increases the manufacturing cost. become.

■ It is difficult to employ RIE processing for finer upper layer wiring for the following two reasons. Therefore, conventional semiconductor devices use wet etching for etching upper layer wiring, making it difficult to meet the demands for higher density. could not.

(a) When RIE is performed on the metal film for upper layer wiring (AI-Cu), as shown in FIG. The thickness of the insulating film is 40% or less of the thickness of the insulating film in the field part, 1600 mm, to stabilize the BT characteristics.
After that, P-5iN is placed on top of the upper layer wiring 6.
P-3i is deposited as the final protective film, but P-3i is already deposited on the lower layer wiring 3 as an interlayer insulating film.
In addition to the N film, a P-8iN film is further laminated as a final protective film, so the lower wiring 3 is covered with a significantly thicker P-8iN film than the field portion.

However, as described above, since the internal stress of the P-8iN film is high, the thicker the P-8iN film covering the lower layer wiring 3 is, the more the defective portion 3a as shown in FIG.
The risk of this occurring increases.

(b) Metal film (AI or A) for forming upper layer wiring by RIE method
1 alloy) □The etching gas is a chlorine-based gas, and this chlorine-based gas is easily adsorbed into the organic insulating film remaining under the upper layer wiring 6 and in the field area. The probability that the upper layer wiring 6 will be corroded by the chlorine-based gas increases.

■ After the upper layer wiring is formed, due to a sudden temperature change, the moisture absorbed in the organic insulating film 5 is gasified and released to the lower side of the upper layer wiring 6 as shown in FIG. 6, and as a result, the upper layer wiring 6 causes bubbling 6A. Therefore, in order to suppress this bubbling, it is necessary to
In the process leading up to film formation, a long period of time (more than 1 hour) is required for moisture removal before high temperature (300°C or more) heat treatment.
However, such operations reduce productivity.

(2) To form through holes, the inorganic insulating film 4 is etched after the organic insulating layers 1 to 5 are etched. However, since the thickness of the organic insulating film varies due to flattening, over-etching must be performed by 80% of the average thickness.

Furthermore, the etching rate ratio of positive resist and organic insulating film in RIE is (resist): (organic insulating film)
-1:0.7, and the etching rate of the organic insulating film is lower than that of the resist. Therefore, if an organic insulating film is over-etched by 80% using a positive resist mask, the holes in the resist mask will expand by about 1.0 μm on one side after the organic insulating film is etched. Since the holes in the inorganic insulating film will be drilled based on
The extent will be expanded. Therefore, in conventional semiconductor devices, it is difficult to miniaturize through holes, and ultimately it is impossible to miniaturize upper layer wiring.

[Object of the Invention] The present invention was made to solve the problems that exist in the conventional semiconductor device as described above, and the purpose of the invention is to flatten the wiring as well as flatten the lower layer wiring and the upper layer wiring. It is an object of the present invention to provide a semiconductor device which is free from wiring defects, has an upper layer wiring which is finer than the conventional one, and has high reliability.

[Summary of the Invention] A semiconductor device according to the present invention is characterized in that it includes a wiring interlayer insulating film having a laminated structure in which the lower layer is a heat-resistant organic insulating layer and the upper layer is a plasma chemical vapor deposition inorganic insulating layer. It is something. In the semiconductor device of the present invention having the multi-station wiring structure, which is equipped with an insulating film having this structure, the flattening effect of the conventional device is not impaired, and there is no fear of defects occurring in the lower layer wiring and the upper layer wiring. Furthermore, it is possible to form finer upper layer wiring than in conventional devices.

[Embodiments of the Invention] A semiconductor device having a multilayer wiring structure and a method for manufacturing the same according to the present invention will be described below with reference to FIG.

Note that in FIG. 1, the parts indicated by the same reference numerals as in FIG. 3 represent the same parts as those described with respect to the conventional semiconductor device in FIG.

The semiconductor device according to the present invention is manufactured, for example, by the following steps. First, a thermal oxide film 2, which is an insulating layer, is formed on a semiconductor substrate 1 having a plurality of impurity regions except for the impurity regions, and a 1 μl thick layer of lower wiring metal III is formed on the insulating layer 2 by sputtering. (AI-8
i) is deposited, the metal film is etched by RIE using the resist pattern formed on the metal film as a mask, thereby forming a first layer extending to the insulating layer 2, which is provided in the impurity region serving as the lower wiring. A conductive metal layer 3 is formed.

Next, after pre-heating treatment, an organic insulating material (
Polyimide resin insulator) was applied, and then subjected to the prescribed beta treatment (150°C - 30 minutes, 250°C - 60 minutes, 400°C
-60 minutes, all in an N2 atmosphere), thereby forming a heat-resistant organic insulating layer 5 having a thickness of 0.4 μm and covering the insulating layer 2 including the first conductive metal 113. Subsequently, the heat-resistant organic insulation 115 is formed by plasma CVD method.
On top of the inorganic insulating layer 4 made of P-8iN film and having a thickness of 1 μm, plasma-enhanced vapor phase growth was formed (formation conditions were gas flow IS).
i H,/N H3=60/30O5CCI, carrier gas Ar700SOCI, pressure 87Pa, temperature 33
0° C. and RF output of 320 W), the state shown in FIG. 1(a) is obtained.

In this way, the thickness of the organic insulating layer is equal to 0 of the thickness of the inorganic insulating layer.
．． It is desirable to set it to 6 or less. This is because electrical stability can be maintained even after the BT treatment, and if this value is 0.6 or more, the electrical characteristics after the BT treatment may vary.

Next, as shown in FIG. 1(b), a positive resist film with a thickness of 1.6 μl is applied on the inorganic insulating layer 4 and a resist pattern 7 is formed by a conventional method, and then the resist pattern 7 is used as a mask. P-8iN film 4 which is an inorganic insulating layer by RIE method
and the polyimide film 5, which is a heat-resistant organic insulating layer, are continuously etched (the etching conditions are gas flow layer SF, 80SCCO+, pressure 10Pa,
Output 450W, 0 for gas N1 for Boli and Mido membranes
(260 sccm, pressure 2.3 Pa, output 520 W) and windows or through holes 9 for connecting upper and lower wiring are penetrated through both of the insulating films.

Next, the resist pattern 7 is peeled off using an organic solvent, heated, and then sputtered to remove the oxide on the exposed lower wiring surface. A metal film (AI-Cu) for upper layer wiring having a thickness of 1 μm is deposited on the surface of the inorganic insulating film 4, and at the same time, the through holes 9 are filled with the metal film.
Then, by selectively etching the metal film by RIE method, a fine second conductive metal layer 6, which is an upper layer wiring, is formed as shown in FIG. Complete the wiring structure.

In the above embodiment, a polyimide resin-based insulator was used as the heat-resistant organic insulating layer, and P-
Although the 8i N film is used, the constituent materials of the organic insulating layer and the inorganic insulating layer do not need to be limited to these, and various materials can be used for each. Similarly, the constituent components of the lower layer wiring and upper layer wiring are Al-8i, Al-Cu, etc.
It goes without saying that it may be made of not only alloys but also other materials such as silicide, high melting point metals, and metals such as pure A1. Furthermore, although continuous RIE was used for etching each layer of the through hole 9 in the laminated insulating film, RIE
Other etching methods such as chemical dry etching and wet etching may be used for each layer individually, and it has been confirmed that the main effects of the above embodiments can be achieved in these cases as well.

[Effects of the Invention] Effects obtained by the semiconductor device of the present invention are listed below.

(I) Since the lower layer wiring is covered with an inorganic insulating layer via a heat-resistant organic insulating layer, there is no risk that the lower layer wiring will be destroyed by the internal stress of the inorganic insulating layer, so it has high electromigration resistance and there is no risk of disconnection. A semiconductor device with a small amount of noise can be obtained.

(I) Since the upper layer wiring is formed on the inorganic insulating layer, the deterioration of the insulating film due to harsh wiring formation conditions is much less than that of the organic insulating layer, which causes short circuits and leaks between the upper layer wiring. There is no danger. Further, since the deterioration does not occur, there is no need for a process for removing the deterioration layer, and therefore the manufacturing process is shortened.

(DI) Since the organic insulating layer is protected by the inorganic insulating layer, no altered layer is formed on the organic insulating layer even if Ar sputtering is performed before forming the upper layer wiring.
Therefore, a semiconductor device can be obtained in which there is no drop in the surface inversion threshold voltage of the non-element region and the variation in the surface inversion threshold voltage is small. Furthermore, a semiconductor device can be obtained in which the fluctuation range of the surface inversion threshold voltage due to the BT process is small, and in particular, the fluctuation range with respect to temperature changes is 3.
Since it is about 0% lower, a highly reliable semiconductor device can be obtained.

(TV> Since the organic insulating layer is under the inorganic insulating layer,
Upper layer wiring can be easily formed using the RIE method.
Therefore, a semiconductor device having finer upper layer wiring and through holes than conventional semiconductor devices can be obtained.

(V) After the inorganic insulating film is formed, the organic insulating film is not exposed to the outside, so there is no adsorption of moisture or chlorine to the organic insulating film, so there is no need for low-temperature baking treatment to remove moisture. Since no altered layer is formed on the surface of the film or resist, there is no need for a process to remove the altered layer, so semiconductor devices can be manufactured in a shorter process than conventional methods, and as a result, semiconductor devices can be manufactured using shorter steps than conventional methods. It is possible to manufacture a semiconductor device with higher reliability than before at a lower cost than before.

Furthermore, when the laminated insulating film of the present invention is an interlayer insulating film, it is particularly effective as explained above, but it is clear that an insulating film having the same laminated structure as the present invention can be used as the final protective film. .

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the semiconductor device of the present invention and its manufacturing method in order of process, FIG. 2 is a cross-sectional view of the main part of a conventional semiconductor device, and FIG. 4(a) is a plan view showing defects occurring in the wiring of a conventional semiconductor device, and FIG. 4(b) is a plan view showing defects occurring in the wiring of a conventional semiconductor device.
), FIG. 5 is a diagram showing phenomena that may occur in the manufacturing process of conventional semiconductor devices, and FIG. 6 is a diagram showing wiring defects that occur in the manufacturing process of conventional semiconductor devices. be. 1... Semiconductor substrate, 2... Insulator layer, 3...
First conductive metal layer (lower wiring), 4... Plasma-enhanced chemical vapor deposition inorganic insulating layer, 5... Heat-resistant organic insulating layer, 5A... Altered layer, 6... Second conductive layer Metal layer (upper layer wiring), 7... Resist pattern, 8°9
...Window (through hole). Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a plurality of impurity regions of opposite conductivity type introduced into the interior from this one main surface, an insulating layer formed on one main surface of the semiconductor substrate excluding the impurity regions, and the impurity a first conductive metal layer provided in a region and extending to the insulating layer; a heat-resistant organic insulating layer covering the insulating layer including the first conductive metal layer; and a heat-resistant organic insulating layer laminated on the heat-resistant organic insulating layer. a plasma-enhanced chemical vapor deposition inorganic insulating layer;
a window that penetrates the inorganic insulating layer and the heat-resistant organic insulating film to expose the first conductive metal layer; and a second conductive metal layer provided in the window.
1. A semiconductor device comprising: a conductive metal layer.