JPH07106323A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve stress migration withstand of electrode wiring, by forming a second insulating film which covers the side surface of the electrode wiring and has compression stress, and a third insulating film which covers the surface of the electrode wiring and has tensile stress. CONSTITUTION:A first silicon oxide film 2 (first insulating film) forms either field oxide film or an interlayer insulating film which are formed by a thermal oxidizing method. A second silicon oxide film 4A having compression stress is formed on electrode wiring 3A and the first silicon oxide film 2. By etching back the second silicon oxide film 4A, it is left on only the electrode wiring side wall part, and a spacer 4Aa having a forward taper shape is formed. A silicon oxynitride film 5A as a third insulating film which has tensile stress is formed. Generation of stress migration can be restrained by the mutual buffering action of the compression stress of the insulating spacer 4Aa and the tensile stress of the silicon oxynitride film 5A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having fine electrode wiring and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional semiconductor device is disclosed in JP-A-63-164.
A structure as shown in Japanese Patent No. 344 is known. Figure 2
(A)-(d) is process order sectional drawing for demonstrating this conventional semiconductor device along with the manufacturing process.

First, as shown in FIG. 2A, after forming a first silicon oxide film 2 on a silicon substrate 1, electrode wiring 3 is formed.
Form B.

Subsequently, as shown in FIG. 2B, a second silicon oxide film 4B having a compressive stress is formed by plasma CVD or sputtering so as to cover the electrode wiring, and a photoresist film 6 is formed thereon. It is formed by a coating method.

Further, as shown in FIG. 2C, the photoresist film and the second silicon oxide film above the electrode wiring are removed by the reactive ion etching method. Thus, the spacer 4Ba filling the space between the electrode wirings 3B is formed.

Next, the photoresist film left unremoved in this step is removed. Further, as shown in FIG. 2D, a third silicon oxide film 5B having a tensile stress is formed by a plasma CVD method, a low pressure CVD method or an atmospheric pressure CVD method.

In addition to the above-mentioned invention, JP-A-3-16782
There is one described in Japanese Patent Publication No. 8. This prior art will be described by taking as an example the case where it is applied to an insulating protective film of a silicon gate MOS memory. First, as shown in FIG. 3A, the diffusion layer 7 formed on the silicon substrate 1 and the electrode wiring 3C made of an aluminum alloy film containing about 1% of silicon or copper are the field oxide film 8 and the first silicon oxide film. A structure is formed which is joined through the contact hole 9 opened in 2. Furthermore, with a single-wafer CVD apparatus,
TEOS [Si at 380 ° C. and a pressure of 10 Torr or less
(O ₂ H ₃ O) ₄ ] and O ₂ are plasma-reacted to about 50
A second silicon oxide film having a thickness of 0 nm is formed, and the second silicon oxide film at 450 ° C.
Heat treatment is performed for 20 to 30 minutes in an Ar atmosphere of% H ₂ .
Next, the spacer 4Ca of the second silicon oxide film is formed by etching back by reactive dry etching using a mixed gas containing C ₂ F ₆ and CHF ₃ .

Then, as shown in FIG. 3B, SiH ₄ ,
PSG that reacts with O ₂ and PH ₃ to form the first protective film
The film 5C is grown to a thickness of 500 nm.

Then, as shown in FIG. 3C, SiH ₄ ,
Using a gas containing NH ₃ and N ₂ , 370 ° C., 5 Torr
Thickness of about 6 by parallel plate plasma CVD equipment under the conditions of
A silicon nitride film 10 serving as a second protective film having a thickness of 00 nm is formed, and a bonding pad 11 for extracting an external electrode is further formed by a dry etching method using a photoresist.
To form.

[0010]

Problems to be Solved by the Invention JP-A-63-1643
In the case of the invention disclosed in Japanese Laid-Open Patent Publication No. 44-44, the spacer 4Ba filling the space between the electrode wirings is formed by the CVD method and the etch back method. However, this method has a wide wiring space which is not affected by the overhang shape of the CVD film. This is an effective method only for. When applied to a fine wiring space where there is a high possibility of occurrence of disconnection due to stress migration and a preventive measure for it is required, voids in the CVD film are formed during the formation of the CVD film due to the overhang shape of the CVD film. The presence of voids in the CVD film reduces the stress relaxation effect that causes stress migration, which is the original function of the spacer, and is therefore difficult to apply to a fine wiring pattern.

In the case of the invention disclosed in Japanese Patent Laid-Open No. 3-167828, organosilane (TEOS) is formed on the side wall of the electrode wiring.
A silicon oxide film is formed by a plasma CVD method using a silicon oxide as a source, a spacer is formed by anisotropic etchback, and a silicon oxide film and a silicon nitride film are formed on the silicon oxide film, and the silicon nitride film has a relative dielectric constant. Is higher than that of a silicon oxide film (the relative dielectric constant of the silicon oxide film is about 3.6 to 5 and about 8 for a silicon nitride film, depending on the film formation method), but this causes an increase in interlayer capacitance, resulting in a semiconductor device. Reduce the operating speed of.

[0012]

The semiconductor device of the present invention comprises:
An electrode wiring that selectively covers a predetermined first insulating film on a semiconductor substrate; a second insulating film that covers the side surface of the electrode wiring and has a compressive stress; a surface of the electrode wiring and the second insulating film; And a third insulating film having a tensile stress for covering.

A method of manufacturing a semiconductor device according to the present invention is
A step of forming an electrode wiring selectively covering a predetermined first insulating film on a semiconductor substrate, and exposing at least a surface of the electrode wiring except a side surface after depositing a second insulating film having a compressive stress. It includes a step and a step of forming a third insulating film having a tensile stress on the entire surface.

[0014]

EXAMPLES Next, examples of the present invention will be described.

1 (a) to 1 (d) are sectional views in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, elements such as MOS transistors (not shown) are formed on the silicon substrate 1. The first silicon oxide film 2 (first insulating film) is a representative one of a field oxide film formed by a thermal oxidation method and an interlayer insulating film. Here, for example, SiH ₄ and N
Thickness of about 500 nm by plasma CVD method using ₂ O
It is formed with the thickness of. Next, 10 titanium is added to tungsten.
A titanium-tungsten film having a thickness of 100 to 200 nm and an aluminum film having a thickness of 500 to 1000 nm added by wt% is formed by a sputtering method, and patterned by using a known technique such as a lithography technique and a dry etching technique. An electrode wiring 3A having a width of 600 nm and formed of an aluminum film is formed. The titanium-tungsten film is provided for the purpose of preventing diffusion of aluminum into the active region and suppressing the occurrence of aluminum electromigration and stress migration. The aluminum film serves as the main conductive layer of the electrode wiring, and not only aluminum but also a material having a low electric resistance such as gold, copper or alloys thereof may be used.

Further, as shown in FIG. 1B, a plasma using a plurality of RF power sources having different oscillation frequencies and SiH ₄ , N ₂ O and N ₂ gases is formed on the electrode wiring 3A and the first silicon oxide film. The second insulating film of 5 to 5 is formed by the CVD method.
Second having a 10 × 10 ⁹ dyne / cm ² compressive stress
The silicon oxide film 4A is formed with a thickness of 100 nm, for example. This thickness is set so as not to exceed half of the space between the electrode wirings. When forming this second silicon oxide film, it is possible to change the stress of the formed film from tension to compression by changing the output ratio of two RF power supplies, a high frequency RF power supply and a low frequency RF power supply. . Eg 1
High frequency RF power supply of 3.56MHz and 200 ~ 500KH
When the output ratio of the low frequency RF power source of z is 3: 1 to 4: 1, the flow rate ratio of SiH ₄ gas and N ₂ O gas is 1: 0.5 to.
A silicon oxide film having a stress of the above value can be formed under the condition of 1: 1.5.

Further, as shown in FIG. 1 (c), CF ₄ ,
The second silicon oxide film 4A is etched back by an anisotropic etchback method using a fluorine-based gas such as C ₂ F ₆ or CHF ₃ to leave the spacer 4Aa having a forward tapered shape only on the side wall of the electrode wiring. Form. Furthermore, FIG.
A plurality of Rs having different oscillation frequencies as shown in (d)
A third insulating film of 0.5 to 2 × 10 ⁹ d is formed by a plasma CVD method using an F power source and SiH ₄ , N ₂ O, and NH ₃ gas.
Silicon oxynitride film 5 having tensile stress of yne / cm ²
A is formed to a thickness of 500 to 1000 nm. At this time, a high-frequency RF power source of 13.56 MHz and 200 to 500
Output ratio of low frequency RF power source of KHz is 1-2: 1, SiH
The flow rate ratio of ₄ gas, N ₂ O gas, and NH ₃ gas is 1: 0.5.
~ 1.5: A silicon oxynitride film having a stress of the above value can be formed under the condition of 0.5 to 1.5. When this silicon oxynitride film is formed, the electrode wiring has a forward taper shape as a whole due to the spacers 4Aa on the sidewalls, so that voids are unlikely to occur even in a fine wiring space, and application to a fine semiconductor device is easy. .

In the semiconductor device formed by the above-mentioned method, stress migration can be suppressed by the mutual buffering action of the compressive stress of the insulating film spacer on the side wall of the electrode wiring and the tensile stress of the silicon oxynitride film formed thereabove. . Further, the silicon oxynitride film has a passivation property equivalent to that of the silicon nitride film and has a lower relative dielectric constant than the silicon nitride film. Therefore, the characteristics of the semiconductor device can be improved by reducing the interlayer capacitance, and the long-term reliability of the semiconductor device does not decrease because the passivation property does not change. The semiconductor device of the present invention can be applied regardless of the type of semiconductor device such as MOS or bipolar.

Next, a second embodiment of the present invention will be described.

This embodiment is the same as the first embodiment except that the method of forming the second silicon oxide film is different.

That is, after forming the electrode wiring on the first silicon oxide film, a plurality of RF power sources having different oscillation frequencies, TEOS [SiO ₂ H ₃ O) ₄ ], and ozone (O ₃ ).
Forming a second insulating film by the plasma CVD method using
Second having a 10 × 10 ⁹ dyne / cm ² compressive stress
A silicon oxide film is formed with a thickness of 100 to 300 nm.

[0023] TEOS _{[Si (O 2 H 3 O)} 4 and ozone (O ₃₎ when the plasma CVD method using the coating of the silicon oxide film to the wiring step than with the SiH ₄ based gas (step The coverage was good. Therefore, it is possible to form an insulating film that does not form a cavity in a finer wiring space than in the case of using SiH ₄ system gas.

[0024]

As described above, in the semiconductor device of the present invention, the second insulating film having the compressive stress is provided on the side surface of the electrode wiring, and the third insulating film having the tensile stress is exposed by exposing the surface of the electrode wiring.
By providing the insulating film, it is possible to suppress the stress migration of the electrode wiring due to the mutual buffering effect of the compressive stress and the tensile stress, and thus it is possible to improve the long-term reliability of the semiconductor device.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of the processes, illustrated in FIGS. 1A to 1D for illustrating a first embodiment of the present invention.

FIG. 2 is a view for explaining a conventional example (a) to (d).
FIG. 7 is a sectional view in order of the processes, which is divided into FIGS.

FIG. 3A is a diagram for explaining another conventional example.
It is a process order sectional view divided and shown in (c).

[Explanation of symbols]

 1 Silicon Substrate 2 First Silicon Oxide Film 3A, 3C, 3D Electrode Wiring 4A, 4C Second Silicon Oxide Film 4Aa, 4Ca, 4Da Spacer 5A, 5B Silicon Oxynitride Film 5C Third Silicon Oxide Film 5D PSG Film 6 Photoresist Film 7 Diffusion layer 8 Field oxide film 9 Contact hole 10 Silicon nitride film 11 Bonding pad

Claims (3)

[Claims] 1. An electrode wiring selectively covering a predetermined first insulating film on a semiconductor substrate, a second insulating film covering a side surface of the electrode wiring and having a compressive stress, a surface of the electrode wiring and the A semiconductor device comprising: a third insulating film having a tensile stress, which covers the second insulating film. 2. The semiconductor device according to claim 1, wherein the electrode wiring includes a single-layer or multi-layer conductive film made of aluminum, gold, copper or an alloy thereof. 3. A step of forming an electrode wiring selectively covering a predetermined first insulating film on a semiconductor substrate, and at least a side surface portion of the electrode wiring after depositing a second insulating film having a compressive stress. A method of manufacturing a semiconductor device, comprising: a step of exposing a surface to be removed; and a step of forming a third insulating film having a tensile stress on the entire surface.