JPS61141130A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61141130A JPS61141130A JP26336084A JP26336084A JPS61141130A JP S61141130 A JPS61141130 A JP S61141130A JP 26336084 A JP26336084 A JP 26336084A JP 26336084 A JP26336084 A JP 26336084A JP S61141130 A JPS61141130 A JP S61141130A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- hole
- resist
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a semiconductor device.
従来、工Ｃ，ＬＳＩなどの半導体装置において電極配線
をクロスさせる多層配線構造の揚台、層間絶縁膜にコン
タクトホールを設けるが、この層間絶縁膜の厚さによシ
コンタクトホールが深くなっていた。すなわち第２Ａ図
はたとえばＭＯＳ・ＩＣにおけるソース領域を示すもの
で、基板１１にはイオン注入によシソース領域１２が形
成され、基板上にはフィールド酸化１１１５お工びゲー
ト酸化１１１４が形成されている。上記フィールド酸化
［１１お工びゲート酸化ＦｖＡ１４上に層間絶縁膜とし
てのシリコン窒化ＩＩｇ （Ｓｉ、Ｎ、）１５さらにそ
の上に層間絶縁膜としてのシリコン酸化膜（ｓｉｏｔ）
１６が被覆されている。このソース領域１２にコンタク
トホールをあけるため、レジスト１７によるパターニン
グをおこなう。そしてエッチングにより層間絶縁１１１
１５．１６を除去し、最後にゲート酸化膜１４を除去し
てコンタクトホール１８を形成している（第２Ｂ図）。Conventionally, in semiconductor devices such as PCBs and LSIs, contact holes are provided in the multilayer wiring structure where electrode wiring crosses and in the interlayer insulating film, but the contact holes become deep due to the thickness of the interlayer insulating film. . That is, FIG. 2A shows, for example, a source region in a MOS/IC, in which a source region 12 is formed in a substrate 11 by ion implantation, and a field oxide 1115 and a gate oxide 1114 are formed on the substrate. . The above field oxidation [11] Silicon nitride IIg (Si, N,) as an interlayer insulating film on the gate oxidation FvA14 15 Furthermore, a silicon oxide film (siot) as an interlayer insulating film on top of the above field oxidation [11]
16 are coated. In order to open a contact hole in this source region 12, patterning is performed using a resist 17. Then, by etching the interlayer insulation 111
15 and 16 are removed, and finally the gate oxide film 14 is removed to form a contact hole 18 (FIG. 2B).
上記従来例においてコンタクトホール１８の深さはシリ
コン酸化−１６、窒化膜１５それにゲート酸化膜１４と
の厚さを加えたものとなる。したがってアルミニウムを
用いて電極配線した際、シリコン［１１１６のエツジの
部分で配線が段切れするおそれがあった。In the conventional example described above, the depth of the contact hole 18 is the sum of the thicknesses of the silicon oxide film 16, the nitride film 15, and the gate oxide film 14. Therefore, when wiring electrodes using aluminum, there was a risk that the wiring would break at the edge of silicon [1116].
この発明は上述の従来例における欠点を解決すルモので
、コンタクトホールが深い穴とならず、配線が段切れす
るおそれがない工うにするため。The present invention is intended to solve the above-mentioned drawbacks of the prior art, so that the contact hole does not become a deep hole and there is no risk of the wiring breaking.
眉間絶縁膜のシリコン窒化ｌ１ｌ（Ｓ １ｓＮ４）をス
トッパーとして眉間絶縁膜の７リコン酸化！！１ｉ（Ｓ
ｉＯｘ）をエッチングにより穴明けし、ついでシリコン
ｆｆｌ化膜お工びその下のゲート酸化膜に上記穴明けし
た大工り小さい穴を設け、コンタクトホールに段差をつ
ける半導体装置の製造方法を提供するものである。7-recon oxidation of the glabellar insulating film using silicon nitride l1l (S 1sN4) of the glabellar insulating film as a stopper! ! 1i(S
This invention provides a method for manufacturing a semiconductor device in which a hole is formed by etching a contact hole (iOx), a silicon FFL film is formed, a small hole is formed in the gate oxide film below the hole, and a step is formed in the contact hole. be.
＠１Ａ図において、７リボン基版１上にフィールド酸化
膜２がパターン形成され、イオン注入によりソース領域
５お工びドＶイン領域（図示されていない）とが形成さ
れる。ついでゲート酸化−４を形成した上に眉間絶縁膜
としてのシリコン窒化！Ｉ！ ５ （Ｓ １ｓＮ４）が
被覆され、そして必要な配線パターン構成をした後、さ
らにその上に眉間絶縁膜としてのシリコン酸化膜６が被
覆されている。この状態でコンタクトホールを窓明けす
るために、まずレジスト７によるパターニングをおこな
う。In Figure 1A, a field oxide film 2 is patterned on a seven-ribbon substrate 1, and a source region 5 and a V-in region (not shown) are formed by ion implantation. Next, gate oxide-4 was formed and silicon nitride was applied as an insulating film between the eyebrows! I! 5 (S 1sN4) is coated, and after forming the necessary wiring pattern, a silicon oxide film 6 as a glabella insulating film is further coated thereon. In this state, in order to open a contact hole, patterning is first performed using resist 7.
この際、やや大きめの穴をあける工うにする。そしてシ
リコン酸化ｍ６をエッチングにより除去した後レジスト
も除去する（ｉｇＩ Ｂ図）。再度レジスト８にｚ５パ
ターニングをおこなうが、今度は先程あけた穴の内側で
それニジ小さい穴をあける工うにパターニングするｃｇ
ｔ ｃ図）。つぎにシリコン窒化１ｌＩ５、ゲート酸化
ＰＡ４をエツチングした後レジスト８を除去し、段差が
ついて緩やかに落ち込むコンタクトホール９が形成され
る（第１ ”９図）。この状態からアルミ配線、保ｇ
ｗを形成して半導体装置を完敗する。At this time, make a slightly larger hole. After removing the silicon oxide m6 by etching, the resist is also removed (Fig. igIB). Perform z5 patterning on resist 8 again, but this time pattern it to make a smaller hole inside the hole you just made.CG
tc figure). Next, after etching the silicon nitride 1lI5 and gate oxide PA4, the resist 8 is removed, and a contact hole 9 with a step and a gentle drop is formed (Fig. 1"9). From this state, the aluminum wiring, the
W is formed and the semiconductor device is completely destroyed.
上述の構成よりなる本発明による半導体装置の製造方法
によれば、コンタクト部分に段差のついた断線の訃それ
のないコンタクトホールを形Ｍ、ｆることができ、また
眉間絶縁膜のシリコン窒化膜が、フィールド酸化膜と眉
間絶縁膜の７リコン酸化−との間に設けられているので
、シリコン酸化膜のエツチングの際、７リコ７ ｆｆｌ
化ｇ ｔ−ストッパーとして利用し、精度工〈エツチ
ングすることができる。According to the method for manufacturing a semiconductor device according to the present invention having the above-described structure, it is possible to form contact holes having shapes M and f with a step in the contact portion and without the risk of disconnection, and also to form a silicon nitride film as an insulating film between the eyebrows. is provided between the field oxide film and the 7 silicon oxide film of the glabella insulating film, so when etching the silicon oxide film, 7 silicon 7 ffl
It can be used as a T-stopper and can be precision etched.
第１Ａ図〜第１Ｄ図は本発明の実施例を蜆造工程を追っ
て示す断面図、ｉＺＡ図、第２Ｂ図は従来例の断面図で
ある。
１・・・シリコン基板
２・・・フィールド酸化膜
４・・・ゲート酸化膜
５・・・７リコンｉ化幌
６・・・ノリコン酸化膜
９・・・コンタクトホール
以 上
第１Ａ図
第１Ｃ図
８゜
°１２FIGS. 1A to 1D are cross-sectional views showing an embodiment of the present invention following the manufacturing process, and FIGS. 1A to 2B are cross-sectional views of a conventional example. 1...Silicon substrate 2...Field oxide film 4...Gate oxide film 5...7 Silicon oxide hood 6...Noricon oxide film 9...Contact hole and above Figure 1A Figure 1C 8°°12
Claims (1)
らにその上に層間絶縁膜としてのシリコン窒化膜および
シリコン酸化膜を設け、コンタクトホールの形成におい
ては、上記シリコン窒化膜をストッパーとして層間絶縁
膜のシリコン酸化膜をエッチングにより穴明けし、つい
でシリコン窒化膜およびその下のゲート酸化膜に上記穴
明けした穴より小さい穴をエッチングにより穴明けし、
段差をつけたコンタクトホールを形成することを特徴と
する半導体装置の製造方法。A field oxide film, a gate oxide film, and a silicon nitride film and a silicon oxide film as an interlayer insulating film are provided on the silicon substrate, and in forming a contact hole, the silicon oxide film of the interlayer insulating film is used as a stopper to form a contact hole. A hole is made in the film by etching, and then a hole smaller than the hole made in the above-mentioned hole is made in the silicon nitride film and the gate oxide film thereunder by etching,
A method for manufacturing a semiconductor device characterized by forming a contact hole with a step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26336084A JPS61141130A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26336084A JPS61141130A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61141130A true JPS61141130A (en) | 1986-06-28 |
Family
ID=17388402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26336084A Pending JPS61141130A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61141130A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119210U (en) * | 1987-01-28 | 1988-08-02 | ||
| JPS63119211U (en) * | 1987-01-28 | 1988-08-02 | ||
| JPH01155604A (en) * | 1987-12-11 | 1989-06-19 | Stanley Electric Co Ltd | Solenoid controlling circuit |
| JPH01143120U (en) * | 1988-03-24 | 1989-10-02 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60192330A (en) * | 1984-03-14 | 1985-09-30 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1984
- 1984-12-13 JP JP26336084A patent/JPS61141130A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60192330A (en) * | 1984-03-14 | 1985-09-30 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119210U (en) * | 1987-01-28 | 1988-08-02 | ||
| JPS63119211U (en) * | 1987-01-28 | 1988-08-02 | ||
| JPH01155604A (en) * | 1987-12-11 | 1989-06-19 | Stanley Electric Co Ltd | Solenoid controlling circuit |
| JPH0474843B2 (en) * | 1987-12-11 | 1992-11-27 | ||
| JPH01143120U (en) * | 1988-03-24 | 1989-10-02 |
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