JPS6113669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the relative positional relationship of each layer precisely by oxidizing a polycrystalline layer used for shaping a P<+> layer in a substrate as it is and etching the oxidizing section to form a hole for shaping a P layer and an N layer. CONSTITUTION:Three layer films of an insulating film 32, a semiconductor polycrystalline layer 33 and an insulating film 34 difficult to be oxidized are formed onto a semiconductor substrate 31, and a hole 35 is shaped at a predetermined position. A P<+> layer 36 is formed from the hole 35. The layer 33 is oxidized while using the film 34 as a mask to shape an oxide film 37. The film 34 is removed, a resist film 38 is formed selectively onto the film 37, and a hole 39 is shaped while employing the film 38 and the layer 33 as masks. A P type base body layer 40 and an N type source layer 41 are formed while using the layer 33 as a mask. According to said manufacture, the accuracy of spaces among the end of the layer 36 and the ends of the layer 40 and the layer 41 is determined by the accuracy of oxidation having excellent controllability, and relative positional relationship among the layer 36 and both the layer 40 and the N layer 41 can be formed precisely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device constituting a vertical MO8FET.

[Technical background of the invention and its problems]

FIG. 2 shows a cross-sectional view and an equivalent circuit diagram of a conventional power MO8FET having a vertical MO8 structure. In the figure, 1 is the drain N
type semiconductor substrate, 2 is a P-type base body region, 3 is an N-type source region, 4 is an insulating film, 5 is a semiconductor polycrystalline layer, 6 is an insulating film between the eyebrows, G is a dirt electrode, S is a source electrode, and D is a drain. 7 is a vertical MO8) transistor, 8 is a parasitic transistor, and 9 is a parasitic resistor. As shown in Fig. 2<), the di layer 2 and the source layer 3 are short-circuited by the source electrode S, but from a circuit perspective, the resistor 9 is connected between the paste and collector of the parasitic transistor 8. has been done. In order to prevent the operation of the parasitic transistor 8, it is necessary to reduce the resistance 9.

FIG. 3 shows a conventional method of manufacturing a transistor in which the value of the resistor 9 is reduced. After forming oxide 812 on semiconductor substrate 11 as shown in FIG. 3(a), holes 13 are formed at predetermined positions. Next, an impurity having a conductivity type opposite to that of the substrate 11 is diffused through the hole 13 to form a P+ layer 14 as shown in FIG. 2(b).

After that, oxidation is performed to form an oxide film 1 covering the P layer 14.
Then, as shown in FIG. 3(c), a di region 16 and a source region 17 are formed. 18.19 in the figure
is an insulating film and a semiconductor polycrystalline layer used when forming the regions 16 and 17. Finally, as shown in FIG. 3(d), an interlayer insulating film 20 and an electrode 2 are provided.

As mentioned above, in order to prevent the operation of the parasitic transistor 8, it is desirable that its pace and the value of the resistor 9 between its collectors be as small as possible. That is, it is desirable to make the P+ layer 14 as wide as possible. However, according to the conventional manufacturing method, the size of the hole 13 for forming the P layer 14 is determined by the mask alignment accuracy during the photolithography process, υP+P+alignment accuracy for the hole for layer 4, and the size of the hole 13 for forming the P layer 14.
6. The alignment accuracy of the diffusion holes for forming the N layer 14 must be taken into account when deciding.

In other words, the edge of the P+ layer 14 when it is formed does not form a self-line with respect to the second layer 16 and N layer 17 that will be formed later, and the relative positional relationship between the P layer 14, the second layer 16, and the N layer 17 is It is difficult to form it with high precision.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a vertical MO8
Highly doped layer for preventing parasitic transistor operation in the structure (the P
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the relative positional relationship between a layer (corresponding to the + layer 14), a di layer, and a source layer can be formed with high accuracy.

[Summary of the invention]

In order to achieve the above object, the present invention includes a first step of forming a three-layer film consisting of a first insulating film, a semiconductor polycrystalline layer, and a second insulating film that is difficult to oxidize on a semiconductor substrate; a second step of making a hole for forming an impurity layer in the layer film; a third step of forming a highly concentrated impurity layer of a conductivity type opposite to that of the semiconductor substrate from the hole; and a masking of the second insulating film. a fourth step of oxidizing at least the semiconductor polycrystalline layer; and a fourth step of removing the second insulation M and removing the oxide film formed in the fourth step using at least the semiconductor polycrystalline layer as a mask. 5 and a sixth step of forming P and N type impurity layers using at least the semiconductor polycrystalline layer as a mask.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1(, ), a first insulating film (for example, 5tO2 film) 32, a semiconductor polycrystalline layer 33, and a second insulating film (for example, SLNg, which is difficult to oxidize) are formed on a semiconductor substrate 31.
A three-layer film of No. 4 is formed, and a hole 35 is formed at a predetermined position. Next, as shown in FIG. 1(b), a P layer 36 is formed through the hole 35 by ion implantation or CVD film. Next, the semiconductor polycrystalline layer 33 is oxidized using the second insulating film 34 as a mask, thereby forming an oxide film 37 as shown in FIG. 1(C). Next, as shown in FIG. 1(d), the second insulating film 34 is removed,
After selectively forming a resist film 38 on the oxide film 37, the holes 3 are etched using the resist film 38 and the polycrystalline layer 33 as a mask, as shown in FIG. 1(e).
form 9. Next, using the polycrystalline layer 33 as a mask, the hole 39 is
From, xelon ion implantation, diffusion and phosphorus ion implantation,
P-type pace by doing diffusion? D layer 40 and N
A mold base layer 41 is formed. Thereafter, an interlayer insulating film 42 and an electrode 43 are formed using a conventional method.

According to the above manufacturing method, the polycrystalline layer 33 used for forming the P layer 36 is oxidized as it is, and the oxidized portion is etched to form holes for forming the second layer 40 and the N layer 41.
The spacing accuracy between the edge of the P+ layer 36 and the edges of the second layer 40 and the eighth layer 41 is determined by the oxidation accuracy with good controllability.
The relative positional relationship between the second layer 40 and the eighth layer 41 can be formed with high accuracy, and the P+ layer 36 can be formed widely.

〔Effect of the invention〕

As explained above, according to the present invention, there are advantages such as the ability to accurately form the relative positional relationship with the high-concentration layer top layer for preventing the parasitic transistor operation of the vertical MO8, the -61-stride layer, and the source layer. A method for manufacturing a semiconductor device having the following can be provided.

[Brief explanation of drawings]

FIG. 1 (=) to excellent) is a process explanatory diagram of an embodiment of the present invention, FIG. 2 (&) is a sectional view of a conventional vertical MO8FET,
The same figure (b) is an equivalent circuit diagram, Figure 3 (,) or d)
1 is an explanatory diagram of the manufacturing process of a conventional vertical MO8FET. 31... Semiconductor substrate, 32... First insulating film, 33
... Semiconductor polycrystalline layer, 34 ... Second insulating film, 35
．． 39... Hole, 36... P+ layer, 37... Oxide film, 38... Resist film, 40... Base is T layer,
41... Source layer.

Claims (1)

[Claims] A first step of forming a three-layer film consisting of a first insulating film, a semiconductor polycrystalline layer, and a second insulating film that is difficult to oxidize on a semiconductor substrate, and forming a hole for forming an impurity layer in the three-layer film. a second step, a third step of forming a highly concentrated impurity layer of a conductivity type opposite to that of the semiconductor substrate from the hole;
a fourth step of oxidizing at least the semiconductor polycrystalline layer using the insulating film as a mask; and a fourth step of oxidizing at least the semiconductor polycrystalline layer by removing the second insulating film and oxidizing the oxide film formed in the fourth step. A method for manufacturing a semiconductor device, comprising a fifth step of removing the polycrystalline semiconductor layer as a mask, and a sixth step of forming a P-type and N-type impurity layer using at least the semiconductor polycrystalline layer as a mask.