JPS61135155A - Optical and electronic integrated circuit device - Google Patents
Optical and electronic integrated circuit deviceInfo
- Publication number
- JPS61135155A JPS61135155A JP59257004A JP25700484A JPS61135155A JP S61135155 A JPS61135155 A JP S61135155A JP 59257004 A JP59257004 A JP 59257004A JP 25700484 A JP25700484 A JP 25700484A JP S61135155 A JPS61135155 A JP S61135155A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- electrode
- pin diode
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000005693 optoelectronics Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 239000000835 fiber Substances 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 18
- 239000010931 gold Substances 0.000 description 17
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000011701 zinc Substances 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は光・電子集積回路装置（ＯＢＩＣ）の集積化構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated structure of an opto-electronic integrated circuit device (OBIC).
０ＥＩＣは光デバイスと電子デバイスを同一基板上に集
積化するが、両者の厚さ方向の寸法の相違によって、基
板上に大きな段差を生じ、フォトリソグラフィ工程にお
ける露光の際のピントが合わせ難く、また配線が困難で
ある。0EIC integrates optical devices and electronic devices on the same substrate, but due to the difference in dimension in the thickness direction of the two, a large step is created on the substrate, making it difficult to focus during exposure in the photolithography process. Wiring is difficult.
これに対し、今日非常なスピードで研究開発が行われ、
種々な集積化構造が提藁されている。In contrast, research and development is being conducted at an extremely rapid pace today.
Various integrated structures have been proposed.
また光デバイスとして光検出器を集積化する場合は、受
光部がお互いに干渉したり、受光の際漏れた光が電子デ
バイスに影響を与えることのないように留意することが
必要である。Furthermore, when integrating photodetectors as optical devices, care must be taken to prevent the light receiving sections from interfering with each other and to prevent light leaking during light reception from affecting the electronic device.
以上説明したように０ＢＩＣの集積化において、特に重
要な点は
（１） プレーナ化
（２）素子間分離
（３）漏洩光の除去
で、これらの条件を満足させるため種々複雑なプロセス
の導入が行われている。As explained above, the particularly important points in 0BIC integration are (1) planarization, (2) isolation between elements, and (3) elimination of leakage light.In order to satisfy these conditions, various complicated processes must be introduced. It is being done.
第２図は従来例によるＯＦ、ＩＣの構造を示す基板断面
図である。FIG. 2 is a sectional view of a substrate showing the structure of an OF and an IC according to a conventional example.
図において、左側に光デバイスとしてＰＩＮ（ｐ型半導
体−絶縁体−ｎ型半導体）受光ダイオードが、右側に電
子デバイスとしてＦＥＴ（ｍｌ効果トランジスタ）が形
成されている。In the figure, a PIN (p-type semiconductor-insulator-n-type semiconductor) light receiving diode is formed as an optical device on the left side, and an FET (ml effect transistor) is formed as an electronic device on the right side.
半絶縁性ガリウム砒素（ＳＩ−ＧａＡｓ）基板２１上に
、ｎ０型ＧａＡｓ （ｎ ”−ＧａＡｓ）層２２、ｎ−
型ＧａＡｓ（ｎ−−ＧａＡｓ）層２３、高抵抗アルミニ
ウムガリウム砒素（ＨＲ−Ａｌｏ、 ３ｃａＯ，？＾Ｓ
）層２４、アンドープＧａＡｓ層２５、ｎ−ＧａＡｓ層
２６を順次被着され、これらの各層にデバイスが形成さ
れている。On a semi-insulating gallium arsenide (SI-GaAs) substrate 21, an n0 type GaAs (n''-GaAs) layer 22, an n-
type GaAs (n--GaAs) layer 23, high resistance aluminum gallium arsenide (HR-Alo, 3caO, ?^S
) layer 24, undoped GaAs layer 25, and n-GaAs layer 26 are sequentially deposited, and devices are formed in each of these layers.
ｎ−ＧａＡｓ層２６とアンドープＧａＡｓ層２５をパタ
ーニングしてＦＥＴ形成領域を残し、ここにゲート電極
Ｇ、ソース電極Ｓ、ドレイン電極りを形成してＦＥＴが
構成されている。なお通常のりソゲラフイエ程に″より
ＦＥＴ領域以外の基板表面は窒化珪素（ＳｉｓＮ＊）層
２７で覆われている。The n-GaAs layer 26 and the undoped GaAs layer 25 are patterned to leave an FET formation region, and a gate electrode G, a source electrode S, and a drain electrode are formed in this region to form an FET. Note that the surface of the substrate other than the FET area is covered with a silicon nitride (SisN*) layer 27 due to the normal adhesive process.
ＰＩＮダイオードのｐ型側電極形成部のＨＲ−ＡＩｏ、
３Ｇａｏ、 ｙＡｓ層２４にくぼみが形成され、ここ
にｎ−ＧａＡｓ層２３に届くように亜鉛（Ｚｎ）を拡散
してｐ型層２８が形成され、この層はｐ型側電極として
の金／亜鉛／金（Ａｕ／Ｚｎ／Ａｕ）層２９、金／クロ
ム（Ａｕ／Ｃｒ）層３０に接続され、さらにｐ型側電極
はＦＥＴのゲート電極Ｇにアルミニウム（Ａ１）配線３
１により接続されている。HR-AIo of the p-type side electrode forming part of the PIN diode,
A depression is formed in the 3Gao, yAs layer 24, and a p-type layer 28 is formed by diffusing zinc (Zn) therein so as to reach the n-GaAs layer 23, and this layer is made of gold/zinc as a p-type side electrode. /gold (Au/Zn/Au) layer 29 and gold/chromium (Au/Cr) layer 30, and the p-type side electrode is connected to the gate electrode G of the FET with aluminum (A1) wiring 3.
1.
またＰＩＮダイオードのｎ型側電極は、エツチングによ
りｎゝ−ＧａＡｓ層２２を露出させ、ここに金／金ケル
マニウム（Ａｕ／＾ｕＧｅ）層３２が形成されている。Further, the n-type side electrode of the PIN diode is etched to expose the n-GaAs layer 22, and a gold/gold kermanium (Au/^uGe) layer 32 is formed thereon.
ＰＩＮダイオードとＦＢＴの分離はＡＩ配線３１の下に
掘られたトンネル３３によりなされている。The PIN diode and FBT are separated by a tunnel 33 dug under the AI wiring 31.
従来の０ＥＩＣは、集積化に際し基板に段差を生じ平坦
化が困難で、また配線下のトンネルによる素子間分離は
その形成が難しく、信顔性の面でも問題である。またＰ
ＩＮダイオードとＦＥＴが同一面上に形成されているた
め、漏洩光の影響を受けやすい。Conventional 0EICs create steps on the substrate during integration, making it difficult to planarize them. Also, it is difficult to form isolation between elements by means of tunnels under wiring, which also poses problems in terms of reliability. Also P
Since the IN diode and FET are formed on the same surface, they are susceptible to leakage light.
上記問題点の解決は、基板表面に光検出器と電子デバイ
ス形成層を順次被着し、該基板の裏面に該光検出器の受
光部電極を形成し、該基板の表面に該光検出器の他方の
電極と電子デバイスを形成してなる本発明による光・電
子集積回路装置により達成される。The above problem can be solved by sequentially depositing a photodetector and an electronic device forming layer on the surface of the substrate, forming a light-receiving part electrode of the photodetector on the back side of the substrate, and forming the photodetector on the surface of the substrate. This is achieved by the opto-electronic integrated circuit device according to the present invention, which forms an electronic device with the other electrode of .
さらに、前記受光部電極が該基板のくぼみに形成される
と、ここに光ファイバの終端を挿入することにより、漏
洩光の影響を除去することができる。Furthermore, when the light receiving electrode is formed in the recess of the substrate, the influence of leaked light can be removed by inserting the terminal end of the optical fiber here.
本発明によれば、ＰＩＮダイオードのｎ型側電極を基板
表面に、ＦＥＴ（厚さ方向の寸法は小さい）と同一面内
に形成して基板の平坦化を可能とし、従って素子間分離
は浅い絶縁領域、または溝により容易にできる。According to the present invention, the n-type side electrode of the PIN diode is formed on the substrate surface in the same plane as the FET (the dimension in the thickness direction is small), making it possible to flatten the substrate, and therefore, the isolation between elements is shallow. This is facilitated by an insulating region or groove.
さらにＰＩＮダイオードのｎ型側電極は基板裏面に形成
されるので、ＦＥＴは漏洩光の影響を受けることなく、
しかもくぼみの深さは各層より桁外れに深い基板の厚さ
に等しく、光ファイバを深く挿入して結合できるため、
隣接する受光部との干渉が避けられる。Furthermore, since the n-type side electrode of the PIN diode is formed on the back surface of the substrate, the FET is not affected by leakage light.
Moreover, the depth of the recess is equal to the thickness of the substrate, which is an order of magnitude deeper than each layer, allowing optical fibers to be inserted deeply and coupled.
Interference with adjacent light receiving sections can be avoided.
第１図（ａ）乃至（ｄ）は本発明による０ＥＩＣの構造
′を工程順に示す基板断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a substrate showing the structure of an 0EIC according to the present invention in the order of steps.
第１図（ａｌにおいて、■は厚さ０．１〜０．２．ｕｎ
（７）ｎ”−ＧａＡｓ層、２は厚さ０．２〜０．３ｐ
ｍのｎ−ＧａＡｓ層、３は厚さ２〜３ｕｍのｎ−ＧａＡ
ｓ層、４はＸ −０，３〜０．４の０Ｒ−ＡＩ、ＩＧａ
＋−ｘＡｓ層、５は５ｒ−ＧａＡａ基板である。Figure 1 (in al, ■ indicates thickness 0.1~0.2.un
(7) n''-GaAs layer, 2 has a thickness of 0.2 to 0.3p
3 is an n-GaAs layer with a thickness of 2 to 3 um.
s layer, 4 is X -0, 0R-AI of 3 to 0.4, IGa
+-xAs layer, 5 is a 5r-GaAa substrate.
第１図中）において、ＰＩＮダイオード受光部の５Ｉ−
ＧａＡｓ基板５を除去してくぼみ６を形成して、ＨＲ−
＾１．ｌＧａ＋−、Ａｓ層４を露出させ、ここにｎ−Ｇ
ａＡｓ層３に届くようにＺｎを拡散してｐ型層７が形成
される。(in Fig. 1), 5I- of the PIN diode light receiving section
The GaAs substrate 5 is removed to form a recess 6, and the HR-
^1. The lGa+-, As layer 4 is exposed, and the n-G
A p-type layer 7 is formed by diffusing Zn so as to reach the aAs layer 3.
基板５の裏面に設けるくぼみを直径１２５μｍ程度の穴
にすると、外径１２５μｍのファイバを深く挿入して結
合することができる。If the recess provided on the back surface of the substrate 5 is a hole with a diameter of about 125 μm, a fiber with an outer diameter of 125 μm can be deeply inserted and coupled.
第１図（Ｃ）において、８は硼素（Ｂ）等のイオンを注
入して形成された素子間分離用の絶縁領域である。また
素子間分離にエツチングにより形成される溝を用いても
よい。いずれにしても絶縁領域８は極めて浅く、その形
成は容易である。In FIG. 1C, reference numeral 8 denotes an insulating region for isolation between elements formed by implanting ions such as boron (B). Alternatively, grooves formed by etching may be used for element isolation. In any case, the insulating region 8 is extremely shallow and easy to form.
第１図（ｄｌにおいて、ＦＥＴ形成領域にゲート電極Ｇ
、ソース電極Ｓ、ドレイン電極りが形成されている。In Figure 1 (dl), the gate electrode G is placed in the FET formation region.
, a source electrode S, and a drain electrode are formed.
Ａｕ／ＡｕＧｅ層９はｎ”−ＧａＡｓ層１上に形成され
たＰＩＮダイオードのｎ型側電極、Ａｕ／Ｚｎ／Ａｕ層
１０と、Ａｕ／Ｃｒ層１１はＺｎｎ拡散型型層７上形成
されたＰＩＮダイオードのｐ型側電極である。The Au/AuGe layer 9 is the n-type side electrode of the PIN diode formed on the n''-GaAs layer 1, the Au/Zn/Au layer 10 and the Au/Cr layer 11 are formed on the Znn diffusion type layer 7. This is the p-type side electrode of the PIN diode.
１２はｐ型側電極とＦＥＴのゲート電極Ｇを接続するＡ
Ｉ配線である。12 is A that connects the p-type side electrode and the gate electrode G of the FET.
This is I wiring.
実施例では、ＧａＡｓについての層構成を述べたが、イ
ンジウム燐（ＩｎＰ）の場合は１にｎ ”−１ｎＧａＡ
ｓ層、２にｎ−ＩｎＰ層、３にｎ−ＩｎＧａＡｓ層、４
に５Ｉ−ＩｎＰ層、５に５ｌ−ＩｎＰ基板を用いると本
発明は適用可能である。In the example, the layer structure for GaAs was described, but in the case of indium phosphide (InP), the layer structure is 1 to n''-1nGaA.
s layer, 2 an n-InP layer, 3 an n-InGaAs layer, 4
The present invention is applicable if a 5I-InP layer is used for 5 and a 51-InP substrate is used for 5.
以上詳細に説明したように本発明によれば、０ＥＩＣの
集積化に際し、基板に段差を生じることなく平坦化が容
易で、また素子間分離は浅いイオン注入層、または溝に
よってできるため、その形成は容易である。さらにＰＩ
ＮダイオードとＦＥＴが反対面上に形成されているため
、漏洩光の影響を受けることはない。As described in detail above, according to the present invention, when integrating an 0EIC, it is easy to planarize the substrate without creating a step, and since isolation between elements can be done by a shallow ion implantation layer or groove, the formation of is easy. Further PI
Since the N diode and FET are formed on opposite sides, they are not affected by leakage light.
第１図（ａ）乃至（ｄｌは本発明による０ＥＩＣの構造
を工程順に示す基板断面図、
第２図は従来例による０ＢＩＣの構造を示す基板断面図
である。
図において、
１はｎ”−ＧａＡｓ層、 ２はｎ−ＧａＡｓ層、３は
ｎ−ＧａＡｓ層、
４はＨＲ−Ａ１．Ｇａ１．Ａｓ層、
５は５ｒ−ＧａＡｓ基板である。
６はくぼみ、 ７はＺｎｎ拡散型型層８は絶縁
領域、
９はｎ型側電極でＡｕ／ＡｕＧｅ層、
１０、１１はｐ型側電極でそれぞれＡｕ／Ｚｎ／Ａｕ層
、Ａｕ／Ｃｒ層、
１２はＡ１配線、
Ｇはゲート電極、 Ｓはソース電極、Ｄはドレイン
電極
許・２５１１
手続補正書彷力
Ｉ年月日
、事件の表示
昭和５９年特許願第２５７００４号
ｉ、補正をする者
事件との関係 特許出願人
住所 神奈川県用崎市中原区上小田中１０１５番地（５
２２）名称富 士 通 株 式 会 社１、代理人
住所 神奈川県川崎市中原区上小田中１０１５番地富士
通株式会社内
５、補正命令の日付FIGS. 1(a) to (dl) are cross-sectional views of a substrate showing the structure of an 0EIC according to the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a substrate showing the structure of an 0BIC according to a conventional example. 2 is an n-GaAs layer, 3 is an n-GaAs layer, 4 is an HR-A1.Ga1.As layer, 5 is a 5r-GaAs substrate. 6 is a depression, 7 is a Znn diffusion type layer 8 is a Insulating region, 9 is the n-type side electrode with Au/AuGe layer, 10 and 11 are the p-type side electrodes with Au/Zn/Au layer and Au/Cr layer respectively, 12 is the A1 wiring, G is the gate electrode, S is the source Electrode, D is the drain electrode. 2511 Procedural amendment letter I date, case indication 1982 Patent Application No. 257004 i, person making the amendment Relationship to the case Patent applicant address Nakahara, Yozaki City, Kanagawa Prefecture 1015 Kamiodanaka (5
22) Name: Fujitsu Co., Ltd. Company 1, Agent Address: 5, Fujitsu Limited, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Date of Amendment Order
Claims (2)
被着し、該基板の裏面に該光検出器の受光部電極を形成
し、該基板の表面に該光検出器の他方の電極と電子デバ
イスを形成してなることを特徴とする光・電子集積回路
装置。(1) A photodetector and an electronic device forming layer are sequentially deposited on the surface of the substrate, a light receiving electrode of the photodetector is formed on the back surface of the substrate, and the other electrode of the photodetector is formed on the surface of the substrate. An optical/electronic integrated circuit device characterized in that it is formed by forming an electronic device with.
ることを特徴とする特許請求の範囲第１項記載の光・電
子集積回路装置。(2) The opto-electronic integrated circuit device according to claim 1, wherein the light receiving electrode is formed in a recess of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59257004A JPS61135155A (en) | 1984-12-05 | 1984-12-05 | Optical and electronic integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59257004A JPS61135155A (en) | 1984-12-05 | 1984-12-05 | Optical and electronic integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61135155A true JPS61135155A (en) | 1986-06-23 |
Family
ID=17300383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59257004A Pending JPS61135155A (en) | 1984-12-05 | 1984-12-05 | Optical and electronic integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61135155A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124583A (en) * | 1986-11-14 | 1988-05-28 | Hitachi Ltd | Semiconductor light receiving device |
| US5357121A (en) * | 1991-10-14 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Optoelectronic integrated circuit |
-
1984
- 1984-12-05 JP JP59257004A patent/JPS61135155A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124583A (en) * | 1986-11-14 | 1988-05-28 | Hitachi Ltd | Semiconductor light receiving device |
| US5357121A (en) * | 1991-10-14 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Optoelectronic integrated circuit |
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