GB2168528A - PIN-diode and FET - Google Patents

PIN-diode and FET Download PDF

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Publication number
GB2168528A
GB2168528A GB08431717A GB8431717A GB2168528A GB 2168528 A GB2168528 A GB 2168528A GB 08431717 A GB08431717 A GB 08431717A GB 8431717 A GB8431717 A GB 8431717A GB 2168528 A GB2168528 A GB 2168528A
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Prior art keywords
fet
region
diode
substrate
pin
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Granted
Application number
GB08431717A
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GB8431717D0 (en
GB2168528B (en
Inventor
George Horace Brook Thompson
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STC PLC
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STC PLC
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Priority to GB08431717A priority Critical patent/GB2168528B/en
Publication of GB8431717D0 publication Critical patent/GB8431717D0/en
Publication of GB2168528A publication Critical patent/GB2168528A/en
Application granted granted Critical
Publication of GB2168528B publication Critical patent/GB2168528B/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

In a monolithically integrated PIN photodiode and field effect transistor (FET) structure, the n region (2) of the PIN-diode is embedded by liquid phase epitaxy in a semi-insulating substrate (5) and the FET layers (6,7) are grown epitaxially on top. Localised zinc diffusion (4) is used to form the p region of the PIN- diode and to connect it to the gate of the FET whilst isolating it from the channel of the FET. The gate can also be connected to a resistive layer (bias resistor), disposed on the substrate, by localised zinc diffusion. In another arrangement a groove is formed adjacent the diode to facilitate connection to the n+ diode region 1. <IMAGE>

Description

SPECIFICATION Photo-detector integrated circuit This invention relates to photo-detector integrated circuits and in particular, although not exclusively, to circuits suitable for operation in optical fibre systems. Typically photodetection in such systems relies on the use of avalanche photodiodes or upon the combination of a PIN diode and a field effect transistor (PIN-FET combination) in which the output of the PIN diode is fed to the gate of an FET.
One of the limitations of a PIN-FET combination is that set by noise considerations. The noise is proportional to the square root of the sum of the diode capacitance and the FET gate capacitance. Noise is therefore reduced and sensitivity enhanced if either or both of these capacitance values can be reduced.
A PIN-FET photodetector integrated circuit in which the diode and the FET exist as separately distinguishable entities, and in which the diode has a lower capacitance per unit area than the capacitance per unit area of the gate, is disclosed in our co-pending Application No.
8322236 (Serial No. ) (J.C. Greenwood-G.H.B. Thompson 56-32). In that integrated circuit the semiconductive layers from which the diode is constructed are also the layers from which the FET is constructed.
This known structure involves disadvantages owing to requiring the construction from a single layer of n-GalnAs of both a subsidiary part of the channel of the FET and the main part of the depletion region of the PIN. Unless the n layer is very low doped it detracts considerably from the performance of the FET.
It is an object of the present invention to provide an alternative PIN-FET photodetector integrated circuit.
According to one aspect of the present invention there is provided a photodetector integrated circuit incorporating a PIN photodiode (PIN-diode) connected to the gate of a field effect transistor (FET), wherein the n region of the PlN-diode is embedded in a semi-insulating substrate, wherein the FET includes epitaxial semiconductive layers disposed on the substrate, and wherein the p region of the PINdiode is formed by localised zinc diffusion which serves also to connect the p region to the gate and isolate it from the channel of the FET.
According to another aspect of the present invention there is provided a method of manufacturing a photodetector integrated circuit including the steps of etching a recess in a semi-insulating substrate, embedding a n-region of a PIN photodiode (PIN-diode) in the recess by liquid phase epitaxy, depositing epitaxial layers and forming a field effect transistor (FET) therefrom on the substrate and adjacent to the recess, and performing localised zinc diffusion whereby to form the p region of the PIN-diode, to connect the p region to the gate of the FET and to isolate it from the channel of the FET.
Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows, partially sectioned, the monolithic integration of a PIN and a JFET according to one embodiment of the present invention; Figure 2 shows, partially sectioned, the monolithic integration of a PIN and a JFET according to another embodiment of the present invention; Figure 3 shows, partially sectioned, the monolithic integration of a TEGFET (HEMT) and a PIN according to a further embodiment of the present invention, and Figure 4 illustrates, partially sectioned, electrical interconnection of the gate of a JFET with a resistive layer by way of localised zinc diffusion.
The PIN-FET integrated photodetector of Fig. 1 includes a PIN diode comprised by an nelnP buffer layer 1, an n GalnAs region 2 comprising the main part of the depletion region and a p GalnAs region 3 formed by epitaxial layers of the FET and a localised zinc diffusion 4, the PIN diode being substantially formed in a semi-insulating InP substrate 5.
The FET includes an n GalnAs channel layer 6, a p GalnAs gate 7, drain and source contacts 8 and 9 and contact metallisation 10 for the gate. As is apparent from the drawing the output of the PIN diode in response to illumination thereof from beneath, this being possible if the substrate is optically transparent at the wavelength of the illumination of interest, is fed to the gate of the FET which is disposed to one side of the PIN diode.
The structure of Fig. 1 is manufactured as follows.
A recess 11 is etched in the semi-insulating substrate 5 and the n lnP buffer layer 1, which is also employed as the n contact for the PIN diode, formed by ion implantation or as described below.
Liquid phase epitaxy is then employed to provide firstly the ntinp layer 1, if not previously obtained by ion implantation and then the n GalnAs region 2 both embedded in the recess 11. Deposition of the GalnAs layer is carried out until the recess is filled and the surrounding surface covered with the overall surface being substantially planar and then the n GalnAs is etched back to reveal a recess filled with n GalnAs and surrounded by semiinsulting InP. An epitaxial layer 6 of n GalnAs is then grown over the entire surface of the substrate 5 and the embedded PIN regions, and this epitaxial layer is subsequently covered by an epitaxial layer 7 of p GalnAs. The localised zinc diffusion 4 is then performed to form the p region of the PIN diode, to connect it to the gate, formed subsequently, and to isolate it from the channel.The epitaxial layers are etched in a conventional manner to produce the required FET structure the p GalnAs gate however extending, together with its underlying GalnAs layers, here converted to p by the zinc diffusion, as a rib 12 over the filled recess. As will be appreciated Fig. 1 only shows some three quarters of the integrated circuit in order to indicate its internal structure also. Drain and source contacts are formed by conventional means and the gate and PIN provided with the contact metallisation 10. In order to achieve electrical contact to the n+lnP region (buffer layer) 1 it must be exposed by suitable etching.
Whereas the channel layer has been described as of n GalnAs it may alternatively be comprised of n GalnAsP and the gate may be of plnP instead of p GalnAs. A plnP gate may also be employed with an n GalnAs channel if the latter is formed by MOCVD.
The structure of Fig. 2 is substantially the same as that of Fig. 1. However, the n-GalnAs region of the PIN diode is surrounded except where the PIN-gate interconnection is provided, by a moat 13 which exposes the n lnP, thus facilitating contact thereto. One advantage of this moat structure is that it allow the area of the mesa to be precisely defined after growth.
The structure of Fig. 3 is similar to that of Fig. 1, the FET being in this case, however, a TEGFET. The PIN diode is manufactured as before. In this case, however, the epitaxial layers are different. A thick low doped n GalnAs epitaxial layer 14, in which conduction in the TEGFET takes place, is formed directly on the semi-insulating InP substrate 5. A thin completely depleted n lnP or InAIAs epitaxial layer 15 is formed on the layer 14. The layers 14 and 15 are patterned as required. Zinc diffusion is then performed to form the p region of the PIN diode as described with respect to Fig. 1. Further processing is as conventional for a TEGFET. Contact metallisation is applied as required to the PIN p region, source and drain regions and alloyed. Gate metallisation is applied without alloying.Where leads are to be attached, additional metallisation may be applied. As an alternative to using alloyings 14' to contact layer 14 under the source contact, ion implantation may be employed.
Fig. 4 illustrates the interconnection of the gate 16 of an FET to a resistive layer 17 deposited on an exposed part of the substrate 18. Such a connection to a bias resistor of the order of 1MQ is required in a photodetector circuit incorporating a PIN-FET arrange ment. Prior to the manufacture of the FET, as described with reference to Fig. 1, Zn (20) is diffused locally into the wafer through layers 16 and 19 into the substrate 20 such that when the FET is constructed it will electrically connect the gate 16 and the resistive layer 17. The resistive layer is formed subsequently either by the evaporation of an appropriate resistive material onto the substrate or by the localised bombardment of the substrate by protons. Such interconnection by zinc diffusion may be carried out simultaneously with the formation of the p region of a PIN diode as described with reference to Figs. 1 to 3, in fact one end of the gate rib may be connected thereby to the PIN diode whereas the other end is connected to the resistive layer (bias resistor). Thus a high sensitivity optical receiver may be provided by monolithic integration techniques.

Claims (19)

1. A photodetector integrated circuit incorporating a PIN photodiode (PIN-diode) connected to the gate of a field effect transistor (FET), wherein the n region of the PIN-diode is embedded in a semi-insulating substrate, wherein the FET includes epitaxial semiconductive layers disposed on the substrate, and wherein the p region of the PIN-diode is formed by localised zinc diffusion which serves also to connect the p region to the gate and isolate it from the channel of the FET.
2. A photodector integrated circuit as claimed in claim 1, wherein the n region is embedded in a recess in the substrate by liquid phase epitaxy.
3. A photodetector integrated circuit as claimed in claim 2 wherein an nt buffer contact layer is disposed in the recess under an n region, comprising said n region, formed by liquid phase epitaxy.
4. A photodetector integrated circuit as claimed in any one of the preceding claims wherein a rib of the epitaxial layers extends from the gate of the FET to over the n region of the PIN-diode.
5. A photodetector integrated circuit as claimed in claim 4 as appendant to claim 3, wherein the n buffer layer is of InP, the substrate is of InP and the n- region is of GalnAs.
6. A photodetector integrated circuit as claimed in claim 5 wherein the FET is a JFET, and wherein the epitaxial layers comprise an n GalnAs layer disposed on the substrate and a p GalnAs layer disposed on the n GalnAs layer.
7. A photodetector integrated circuit as claimed in claim 5 wherein the FET is a JFET, and wherein the epitaxial layers comprise an n GalnAsP layer disposed on the substrate and a p InP layer disposed on the n GalnAsP layer.
8. A photodetector integrated circuit as claimed in claim 5 wherein the FET is a JFET, and wherein the epitaxial layers comprise an n GalnAs layer disposed on the substrate and a plnP layer disposed on the n GalnAs layer.
9. A photodetector integrated circuit as claimed in any one of claims 4 to 8, and including a moat around the n region of the PIN-diode except where the rib extends to the PIN diode.
10. A photodetector integrated circuit as claimed in claim 5 wherein the FET is a TEG FET, and wherein the epitaxial layers comprise an n-GalnAs layer disposed on the substrate and an n+ InP or InAlAs layer disposed on the n- GalnAs layer.
11. A photodetector integrated circuit as claimed in claim 2, wherein the recess extends into the substrate from one surface thereof and wherein in use the PlN-diode is illuminated from the opposite surface of the substrate.
12. A photodetector integrated circuit as claimed in any one of the preceding claims and including a resistive layer disposed on the substrate and electrically connected to the gate by locallised zinc diffusion.
13. A method of manufacturing a photodetector integrated circuit including the steps of etching a recess in a semi-insulating substrate, embedding a n-region of a PIN photodiode (PlN-diode) in the recess by liquid phase epitaxy, depositing epitaxial layers and forming a field effect transistor (FET) therefrom on the substrate and adjacent to the recess, and performing localised zinc diffusion whereby to form the p region of the PIN-diode, to connect the p region to the gate of the FET and to isolate it from the channel of the FET.
14. A method as claimed in claim 13, including forming a rib of the epitaxial layers to extend from the gate of the FET to the n region of the PIN-diode.
15. A method as claimed in claim 13 or claim 14 including the step of forming contacts to the source and drain of the FET and the n region of the PIN-diode.
16. A method as claimed in claim 15 wherein an n buffer/contact layer is disposed in the recess prior to or during said liquid phase epitaxy step and including the step of contacting said n buffer/contact layer subsequent to said zinc diffusion.
17. A method as claimed in any one of claims 13 to 16 including the step of depositing a resistive layer on the substrate or forming it in the substrate, and electrically connecting it to the gate by localised zinc diffusion.
18. A photodetector integrated circuit substantially as herein described with reference to Fig. 1, Fig. 2 or Fig. 3 with or without reference to Fig. 4 of the accompanying drawings.
19. A method of manufacturing a photodetector integrated circuit substantially as herein described with reference to Fig. 1, Fig. 2 or Fig. 3 with or without reference to Fig. 4 of the accompanying drawings.
GB08431717A 1984-12-15 1984-12-15 Photo detector integrated circuit Expired GB2168528B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08431717A GB2168528B (en) 1984-12-15 1984-12-15 Photo detector integrated circuit

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GB8431717D0 GB8431717D0 (en) 1985-01-30
GB2168528A true GB2168528A (en) 1986-06-18
GB2168528B GB2168528B (en) 1988-07-13

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3712864A1 (en) * 1986-09-01 1988-03-10 Licentia Gmbh Photoreceiver
DE3629684A1 (en) * 1986-09-01 1988-03-10 Licentia Gmbh Photoreceiver
DE3629681A1 (en) * 1986-09-01 1988-03-10 Licentia Gmbh PHOTO RECEIVER
DE3629685A1 (en) * 1986-09-01 1988-03-17 Licentia Gmbh PHOTO RECEIVER
DE3644410A1 (en) * 1986-12-24 1988-07-07 Licentia Gmbh PHOTO RECEIVER
DE3644408A1 (en) * 1986-12-24 1988-07-07 Licentia Gmbh PHOTO RECEIVER
EP0317024A1 (en) * 1987-11-20 1989-05-24 Laboratoires D'electronique Philips Production method of an integrated infrared-photodetector
EP0331103A2 (en) * 1988-02-29 1989-09-06 Sumitomo Electric Industries, Ltd. A method for producing an opto-electronic integrated circuit
GB2228616A (en) * 1989-02-22 1990-08-29 Stc Plc Semiconductor optical receiver circuit
US4982256A (en) * 1987-10-22 1991-01-01 Nec Corporation Optoelectronic integrated circuit
US5170228A (en) * 1988-02-29 1992-12-08 Sumitomo Electric Industries, Ltd. Opto-electronic integrated circuit

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3712864A1 (en) * 1986-09-01 1988-03-10 Licentia Gmbh Photoreceiver
DE3629684A1 (en) * 1986-09-01 1988-03-10 Licentia Gmbh Photoreceiver
DE3629681A1 (en) * 1986-09-01 1988-03-10 Licentia Gmbh PHOTO RECEIVER
DE3629685A1 (en) * 1986-09-01 1988-03-17 Licentia Gmbh PHOTO RECEIVER
DE3712864C2 (en) * 1986-09-01 2001-05-17 Daimler Chrysler Ag Monolithically integrated photo receiver
DE3629685C2 (en) * 1986-09-01 2000-08-10 Daimler Chrysler Ag Photo receiver
DE3644410A1 (en) * 1986-12-24 1988-07-07 Licentia Gmbh PHOTO RECEIVER
DE3644408A1 (en) * 1986-12-24 1988-07-07 Licentia Gmbh PHOTO RECEIVER
US4982256A (en) * 1987-10-22 1991-01-01 Nec Corporation Optoelectronic integrated circuit
US4904607A (en) * 1987-11-20 1990-02-27 U.S. Philips Corp. Method of manufacturing an integrated infrared detector
FR2623664A1 (en) * 1987-11-20 1989-05-26 Labo Electronique Physique METHOD FOR PRODUCING AN INTEGRATED INFRARED PHOTODETECTOR
EP0317024A1 (en) * 1987-11-20 1989-05-24 Laboratoires D'electronique Philips Production method of an integrated infrared-photodetector
EP0331103A3 (en) * 1988-02-29 1990-12-27 Sumitomo Electric Industries, Limited A method for producing an opto-electronic integrated circuit
EP0331103A2 (en) * 1988-02-29 1989-09-06 Sumitomo Electric Industries, Ltd. A method for producing an opto-electronic integrated circuit
US5170228A (en) * 1988-02-29 1992-12-08 Sumitomo Electric Industries, Ltd. Opto-electronic integrated circuit
GB2228616A (en) * 1989-02-22 1990-08-29 Stc Plc Semiconductor optical receiver circuit
GB2228616B (en) * 1989-02-22 1992-11-04 Stc Plc Opto-electronic device

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Publication number Publication date
GB8431717D0 (en) 1985-01-30
GB2168528B (en) 1988-07-13

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