JPS61135143A - Package for transistor - Google Patents

Package for transistor

Info

Publication number
JPS61135143A
JPS61135143A JP25781984A JP25781984A JPS61135143A JP S61135143 A JPS61135143 A JP S61135143A JP 25781984 A JP25781984 A JP 25781984A JP 25781984 A JP25781984 A JP 25781984A JP S61135143 A JPS61135143 A JP S61135143A
Authority
JP
Japan
Prior art keywords
container
metallized layer
leads
layer
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25781984A
Other languages
Japanese (ja)
Inventor
Yukio Kaneko
幸雄 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25781984A priority Critical patent/JPS61135143A/en
Publication of JPS61135143A publication Critical patent/JPS61135143A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To keep hermetic properties by covering the surface of a metallic layer of an outer surface of the container which is connected with the lead which is given a ground potential out of the leads and the part of sealing alloy for sealing the container with a cap with the ceramic thin film. CONSTITUTION:Leads 2 are formed at the bottom of a container 8 and the leads 2 are connected with the elements such as a FET attached in the inside through the through holes. Among the leads, one that is connected to a source electrode and is given a ground potential is connected by a metallized layer 3 on the outer surface of the container 8 up to its upper end. This metallized layer 3 is for preventing a resonance when the cap 4 or the sealing alloy 1 is straying electrically. The center of the metallized layer 3 is coated with a ceramic layer 5 having a thickness of about 50mum. By comprising the ceramic layer 5, a solder 7 is prevented from rising along the metallized layer 3 when the main package is mounted on a printed circuit board or a microwave circuit by soldering. Then the defects such that a hole is made on the sealing alloy 1 or the hermetic properties is deteriorated with aging can be solved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明に、マイクロ波通信に弔いら詐るトランジスター
のパッケージ（容器）に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a package (container) for a transistor used in microwave communication.

〔従来の技術〕[Conventional technology]

従来、マイクロ波トランジスタのパッケージとしてに、
第２図に示されたように、底面にリード２が取り付けら
れた積層セラミックの容器８に金とすすの合金１を用い
てキャップ４が封着されている構造が一般的である。Conventionally, as a package for microwave transistors,
As shown in FIG. 2, a general structure is such that a cap 4 is sealed using an alloy 1 of gold and soot to a laminated ceramic container 8 having a lead 2 attached to the bottom surface.

マイクロ波トランジスターでは第２口封着用合金ｌの部
分が電気的に浮遊しているとこの部分が共振して、発振
等の問題が生ずることがよく知られており、この封着用
合金１の部分とソース電極を取り出すり−ド２とがメタ
ライズ層３で接続されているのが常である。It is well known that in a microwave transistor, if the part of the second sealing alloy 1 is electrically floating, this part will resonate and cause problems such as oscillation. and a lead 2 from which the source electrode is taken out are usually connected by a metallized layer 3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のマイクロ波トランジスタのパッケージは
、ソース電極導出用のリード２と封着用合金１とがメタ
ライズ層３で電気的に結ばれているため、マイクロ波ト
ランジスターをマイクロ波回Ｗ＆６に半田づけにより、
実装する際第３図に示したようにこのメタライズ層３に
沿って半田７が表置張力により封着用合金ｌまではい上
るという現象を生じることがある。In the conventional microwave transistor package described above, the lead 2 for leading out the source electrode and the sealing alloy 1 are electrically connected by the metallized layer 3, so the microwave transistor can be connected to the microwave circuit W&6 by soldering. ,
During mounting, as shown in FIG. 3, a phenomenon may occur in which the solder 7 creeps up along the metallized layer 3 to the sealing alloy 1 due to surface tension.

封着用合金ｌとして使用している金すず合金に半田に含
まれている鉛が混入すると、融点が下がリ、半田づけの
工程中において封着用合金ｌの部分に穴があいたり、長
時間経過するうちに封着用合金１０部分の劣化が進む等
の信頼度に関する欠点があった。If the lead contained in the solder is mixed into the gold-tin alloy used as the sealing alloy, the melting point will drop, and holes may be formed in the sealing alloy during the soldering process, causing long-term damage. There were drawbacks regarding reliability, such as the deterioration of the sealing alloy 10 portion progressing over time.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によるマイクロ波トランジスタ用パッケージでは
、中ヤップを容器に封着する封着用合金の部分とリード
のうち接地電位が与えらｎるものとｔ−接続する容器外
表面の金属層の表面をセラミック薄膜に二っておおって
＾る。In the microwave transistor package according to the present invention, the surface of the metal layer on the outer surface of the container that is T-connected to the part of the sealing alloy that seals the inner cover to the container and the lead that is given a ground potential is made of ceramic. Cover with two thin films.

〔実施例」 次に、本発明について図面を参照して説明する。〔Example" Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の立体図である。容器８０底
面にリード２が形成さｎており、容器８の内部に取り付
けらルるＰＥＴ等の素子とリード、２とはスルーホール
を介して接続されている。リード２のうち接地電位の与
えられるソース電極に接続されるものは容器８の外表面
のメタライズ層３によって上端まで接続されている。容
器８の上端は封着用合金ｌでキャップ４に接着さｎてい
る。FIG. 1 is a three-dimensional diagram of an embodiment of the present invention. A lead 2 is formed on the bottom surface of the container 80, and the lead 2 is connected to an element such as PET mounted inside the container 8 via a through hole. Among the leads 2, those connected to the source electrode to which a ground potential is applied are connected to the upper end by the metallized layer 3 on the outer surface of the container 8. The upper end of the container 8 is adhered to the cap 4 with a sealing alloy.

このメタライズ層３はキャップ４や封着用合金１が電気
的に浮遊状態であると共振して発振を生じるおそれがあ
り、この共振を生じさせないためである。メタライズ層
３の中心５ｔ−Ｚ約５０μ情の厚さ金有するセラミック
層５で被覆されている。This metallized layer 3 is designed to prevent resonance from occurring, which may resonate if the cap 4 or the sealing alloy 1 is in an electrically floating state, causing oscillation. The center 5t-Z of the metallized layer 3 is coated with a ceramic layer 5 having a thickness of about 50μ.

セラミック層５を有することにより、本パッケージ七半
田付けでプリント板やマイクロ波回路に実装する際、第
４図に示したように、メタライズ層３に沿りた半田７の
はい上りが防止される。これによって、封着用合金１に
穴があいたり、気密性が長い間に劣化したりする欠点が
解決された。By having the ceramic layer 5, when this package is mounted on a printed circuit board or a microwave circuit by soldering, the solder 7 is prevented from creeping up along the metallized layer 3, as shown in FIG. . This solves the drawbacks of holes forming in the sealing alloy 1 and deterioration of airtightness over a long period of time.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、マイクロ波パッケージ
の封着用金属ロー材部と固定電位の与えらｎるべきリー
ド部を接続する容器外表面のメタライズ層をセラミック
薄膜でおおうことにより、トランジスタ金外部の回路に
半田付けで実装する際、半田が封着用金属ロー材部には
い上がるのを防止し、気密性を保持できる効果がある。As explained above, the present invention provides a method for forming transistors by covering the metallized layer on the outer surface of the container, which connects the sealing metal brazing part of the microwave package with the lead part to which a fixed potential is applied, with a ceramic thin film. When mounted on an external circuit by soldering, the solder is prevented from creeping into the solder metal part for sealing, and airtightness can be maintained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例によるマイクロ波トランジス
タ用パッケージの斜視図である。 第２図は従来のマイクロ波トランジスタ用パッケージの
斜視図である。 第３図は従来のマイクロ波トランジスタを半田付けによ
り外部の回路に取り付けたときの断面図である。 第４図は本発明の一実施例によるマイクロ波トランジス
タを半田付けにより外部の回路に取り付けたときの断面
図である。 １・・・・・・封着用合金、２・・・・・・リード、３
・・・・・・メタライズ層、４・・・・・・キャップ、
５・・・・・・セラミック被覆、６・・・・・・外部回
路、７・・・・・・半田、８・・・・・・容器。 冷１０ 峯３扇FIG. 1 is a perspective view of a microwave transistor package according to an embodiment of the present invention. FIG. 2 is a perspective view of a conventional microwave transistor package. FIG. 3 is a cross-sectional view of a conventional microwave transistor attached to an external circuit by soldering. FIG. 4 is a sectional view of a microwave transistor according to an embodiment of the present invention when it is attached to an external circuit by soldering. 1...Sealing alloy, 2...Lead, 3
...metalized layer, 4...cap,
5... Ceramic coating, 6... External circuit, 7... Solder, 8... Container. Cold 10 Mine 3 fans

Claims (1)

【特許請求の範囲】[Claims] 　容器のキャップを接着する封着用金属ロー材と固定電
位の与えられるリードとを電気的に接続している前記容
器外表面のメタライズ層がセラミック被膜によりおおわ
れていることを特徴とするトランジスタ用パッケージ。1. A transistor package, wherein a metallized layer on the outer surface of the container that electrically connects a sealing metal brazing material that adheres a cap of the container to a lead to which a fixed potential is applied is covered with a ceramic film.
JP25781984A 1984-12-06 1984-12-06 Package for transistor Pending JPS61135143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25781984A JPS61135143A (en) 1984-12-06 1984-12-06 Package for transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25781984A JPS61135143A (en) 1984-12-06 1984-12-06 Package for transistor

Publications (1)

Publication Number Publication Date
JPS61135143A true JPS61135143A (en) 1986-06-23

Family

ID=17311562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25781984A Pending JPS61135143A (en) 1984-12-06 1984-12-06 Package for transistor

Country Status (1)

Country Link
JP (1) JPS61135143A (en)

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