JPS6146053A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6146053A JPS6146053A JP59167462A JP16746284A JPS6146053A JP S6146053 A JPS6146053 A JP S6146053A JP 59167462 A JP59167462 A JP 59167462A JP 16746284 A JP16746284 A JP 16746284A JP S6146053 A JPS6146053 A JP S6146053A
- Authority
- JP
- Japan
- Prior art keywords
- section
- metallized
- semiconductor device
- bonding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/1617—Cavity coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高周波用小量気密容器を有する半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having a small volume airtight container for high frequency.
（従来の技術）
ＧａＡｓ ＦＥＴを一例にあげると、従来この種の装置
は容器キャップを接着するシール材である合金層がどの
端子にも接続されていない場合、高周波において共振が
発生することが多々ある。このためシール材は一般的に
容器の外側でメタライズ部分を介してソースリード（ソ
ース接地の時）に接続されていた。しかしながらＧａＡ
ａＦＥＴのノースリードをはんだ付する時にはんだの量
が多過ぎたり、はんだ温度が高過ぎたりするとはんだが
メタライズ部分をはい上がりシール材に接触する恐れが
あった。(Prior Art) Taking GaAs FET as an example, in conventional devices of this type, resonance often occurs at high frequencies when the alloy layer, which is the sealing material that adheres the container cap, is not connected to any terminal. be. For this reason, the sealing material is generally connected to the source lead (when the source is grounded) via a metallized portion on the outside of the container. However, GaA
When soldering the north lead of an aFET, if the amount of solder is too large or the solder temperature is too high, there is a risk that the solder will creep up the metallized portion and come into contact with the sealing material.
Ａｕ−８ｎ の合金により完全気密封止された半導体
装置でははんだ（ｐｂ−８ｎ） が接触し、ある温度
に達すると共晶温度に至りシール材が溶融し、気密性が
失われたりｐｂが容器の内側まで及ぶことによりＰｂＫ
よる半導体素子への汚染が発生していた。また大型パッ
ケージでは容器外側メタライズの替りに内側メタライズ
によりＧａＡｓＦＥＴソース部にシール部に接続されて
いる実例はある。In a semiconductor device that is completely hermetically sealed with an Au-8n alloy, solder (PB-8N) comes into contact with the solder, and when it reaches a certain temperature, it reaches the eutectic temperature and the sealing material melts, causing loss of airtightness and PB leaking into the container. By extending to the inside of PbK
Contamination of semiconductor devices has occurred. Furthermore, in large packages, there are actual examples in which the GaAsFET source section is connected to the seal section by means of inner metallization instead of outer metallization of the container.
しかし小量パッケージに前述の内側メタライズを適用し
ようとすると、はんだ付は工程等で溶けたシール材がメ
タライズ部を伝わってボンディング部まで及びボンディ
ングワイヤ剥れあるいはボンディング材料がシール材に
食われてしまう等の問題があった。However, if you try to apply the above-mentioned inner metallization to a small-volume package, the sealant that melts during the soldering process will travel through the metallization part and reach the bonding part, causing the bonding wire to peel off or the bonding material to be eaten by the sealant. There were other problems.
またシール材とリードとの間の外側メタライズ上に何ら
かの材料でコーティングをすることも考えられるがコー
ティング材料がシール材のメタライズ部まで及びシール
強度が弱まったり半導体装置リードまで及びマウント性
が悪くなることが予想される。It is also possible to coat the outer metallization between the sealant and the lead with some kind of material, but the coating material may extend to the metallization of the sealant, weakening the sealing strength, or extend to the semiconductor device leads, resulting in poor mountability. is expected.
（発明が解決しようとする問題点）
本発明の目的はこれらの欠点を除去し、半導体装置を基
板に実装する際はんだ付の条件を緩めリフロ一式はんだ
付のような量産技術が適用でき、高周波特性が優れた半
導体装置を提供することにある。(Problems to be Solved by the Invention) The purpose of the present invention is to eliminate these drawbacks, relax the soldering conditions when mounting semiconductor devices on a board, make it possible to apply mass production techniques such as reflow soldering, and realize high-frequency The objective is to provide a semiconductor device with excellent characteristics.
（問題点を解決するだめの手段）
本発明の半導体装置はその容器の内側にメタライズ部が
設けられ、このメタライズ部がキャップを接着するシー
ル部を介して接地端子と接続されてお９、かつ内側メタ
ライズ部の表面がセラミック膜により部分コーティング
されている。(Means for Solving the Problems) The semiconductor device of the present invention is provided with a metallized portion on the inside of its container, and this metallized portion is connected to a ground terminal through a seal portion to which the cap is bonded. The surface of the inner metallized portion is partially coated with a ceramic film.
（実施列） 次に本発明の実施例を図面を用いて説明する。(Implementation row) Next, embodiments of the present invention will be described using the drawings.
第２図は従来の小量気警容器を用いた半導体装置の断面
図である。シール材２と接地用リード５とを電気的に接
続するため容器の側壁３の外側にメタライズ４を有して
いる。このため、ノ・ンダがリート責接地用リード５以
外のリード）にそってはい上ったり、逆にシール材２が
溶けてメタライズＩＷｔ４にそってリード５に達したり
して、そのリードとシール材２とを短絡してしまうこと
があった。FIG. 2 is a cross-sectional view of a semiconductor device using a conventional small-volume air container. A metallization 4 is provided on the outside of the side wall 3 of the container to electrically connect the sealing material 2 and the grounding lead 5. As a result, the lead may crawl up along the lead (other than the lead for grounding lead 5), or conversely, the seal material 2 may melt and reach the lead 5 along the metallized IWt4, and the lead and seal In some cases, the material 2 was short-circuited.
第１図は本発明の一実施例の断面図である。外側メタラ
イズ部１０はリード近傍のみにあり、半導体装置チンプ
マウント部１１と高さまで形成されている。それに替り
側壁３の内側にメタライズ４が施され接着部２と半導体
７のマウント部１１を介し接地端子であるリード５に接
続されている。FIG. 1 is a sectional view of an embodiment of the present invention. The outer metallized portion 10 is located only in the vicinity of the leads and is formed up to the same height as the semiconductor device chimp mount portion 11. Instead, metallization 4 is applied to the inside of the side wall 3 and connected to a lead 5, which is a ground terminal, via the adhesive part 2 and the mounting part 11 of the semiconductor 7.
側壁内側のメタライズ４の表面はセラミック膜による部
分コーティング１５がされている。The surface of the metallized metallization 4 inside the side wall is partially coated 15 with a ceramic film.
これにより接着部２の接着材がメタライズ部４を紅白し
ボンディングワイヤ８のボンディング部まで流れ落ちる
ことを防ぐことができる。This can prevent the adhesive in the bonding portion 2 from causing the metallized portion 4 to become red and white and flowing down to the bonding portion of the bonding wire 8.
また前述の通りシール部は最終的には接地端子に接続さ
れるため高周波において共撮の発生がなく安定した特性
を有する半導体装置が実現できる。Further, as described above, since the seal portion is ultimately connected to the ground terminal, it is possible to realize a semiconductor device having stable characteristics without occurrence of co-photography at high frequencies.
（発明の効果）
以上説明したように、本発明によれば合金により封止さ
れた小量容器を有する半導体装置において、浸れた高周
波特性が得られるうえ基板への実装の際はんだはい上り
の開運がないため個々に非常に狭い条件下で時間をかけ
慎重にはんだ付する必要がなく、はんだリフロー等の安
価な実装方法が適用できるので半導体装置を使用する装
置メーカーでの原価低減に大きな効果がある。(Effects of the Invention) As explained above, according to the present invention, in a semiconductor device having a small volume container sealed with an alloy, it is possible to obtain immersed high frequency characteristics, and also to improve solder climbing when mounting on a board. There is no need to spend time and carefully soldering each device under very narrow conditions, and inexpensive mounting methods such as solder reflow can be applied, which has a great effect on cost reduction for equipment manufacturers who use semiconductor devices. be.
第１図は本発明の一実施例による半導体装置の断面図、
第２図は従来の半導体装置の断面図である。
１・・・・・・キャップ、２・・・・・・シール部、３
・・・・・・側壁、４・・・・・・メタライズ＃ ５
・−・−・リード、６・・・・・・セラミック、７・・
・・・・半導体素子、８・・・・・・ポンディングワイ
ヤ、１５・・・・・・コーティング用樹脂、２０・・・
・・・メタライズ層、２１・・・・・・半導体素子コウ
ント部。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view of a conventional semiconductor device. 1...Cap, 2...Seal part, 3
...Side wall, 4...Metallization #5
・−・−・Lead, 6... Ceramic, 7...
... Semiconductor element, 8 ... Bonding wire, 15 ... Coating resin, 20 ...
. . . Metallized layer, 21 . . . Semiconductor element count portion.
Claims (1)
、内側に接地端子と電気的に導通させるための側面メタ
ライズ層を有し、かつ該側面メタライズ層の一部がセラ
ミック膜によって部分コーティングを施されていること
を特徴とする半導体装置。A completely airtight small container bonded with a low melting point alloy, which has a side metallized layer on the inside for electrical conduction with a ground terminal, and a part of the side metallized layer is partially coated with a ceramic film. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167462A JPS6146053A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167462A JPS6146053A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6146053A true JPS6146053A (en) | 1986-03-06 |
Family
ID=15850122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59167462A Pending JPS6146053A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6146053A (en) |
-
1984
- 1984-08-10 JP JP59167462A patent/JPS6146053A/en active Pending
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