JPS61134038A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61134038A
JPS61134038A JP25665184A JP25665184A JPS61134038A JP S61134038 A JPS61134038 A JP S61134038A JP 25665184 A JP25665184 A JP 25665184A JP 25665184 A JP25665184 A JP 25665184A JP S61134038 A JPS61134038 A JP S61134038A
Authority
JP
Japan
Prior art keywords
film
oxide film
filled
forming
recesses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25665184A
Other languages
Japanese (ja)
Inventor
Noboru Hirakawa
昇 平川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25665184A priority Critical patent/JPS61134038A/en
Publication of JPS61134038A publication Critical patent/JPS61134038A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To adhere a passivation film with good coverage, and to prevent the generation of cracks by a method wherein the passivation film is formed after aluminum wiring are formed and its recesses and steps are filled with an Si oxide film series film. CONSTITUTION:Similarly to the conventional case, an element-forming region, a gate poly Si electrode, etc. are formed on a substrate 11, and contact holes are bored. Aluminum wirings 14, 15 are formed, and next a coating solution for forming an Si oxide film series film is applied. Then, the Si oxide film 16 is formed by calcination in an N2 atmosphere. Since said coating solution has a low viscosity, the ends of the aluminum wirings 14 and 15 at the contact aperture part are filled with this coating solution. Here, calcination causes it to change into the oxide film series film 16, and at this step the wafer surface becomes gentle because the steps and recesses are filled with this film 16. Thereafter, a passivation film 17 is grown.

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体装置の製造方法に関するもので、特にベ
レット表面の保護膜(以下、バフベージ7)膜と称す)
による信頼性に関するものである。
[Detailed Description of the Invention] (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a protective film on the surface of a pellet (hereinafter referred to as buffage 7 film).
It is about reliability.

(従来技術) 従来技術によるバシベーシ叢ン膜は第1図のようになっ
てい友。第1図で3は絶縁膜、4,5はアルミニウム配
線、6はバシベー7 、7膜である。
(Prior art) The vasibasis membrane according to the prior art is as shown in Fig. 1. In FIG. 1, 3 is an insulating film, 4 and 5 are aluminum wiring lines, and 6 is a base film 7 and 7 film.

すなわち、従来技術では特にコンタクト開孔部7の部分
は凹型になっている為バフベージ−1ノ膜6が薄くなっ
几り、又図示はしていないがバフベージ! 7膜t−成
長する時アルミニウムとバシペーシ!17膜の熱膨張率
の違いからストレスにより亀裂がはいる事もある。この
為ケース(%にグラステックケース)に組み立てt時耐
湿性テストあるいはバイアステスト等の信頼性テスト時
にバシベー7ツノ膜の薄い部分あるいは亀裂の入った部
分で不良となシ信頼性を劣化させてい友。
That is, in the prior art, the part of the contact hole 7 in particular has a concave shape, so the film 6 of the buff page 1 becomes thinner and thicker. 7 film t-Aluminum and basipacity when growing! 17 Cracks may occur due to stress due to differences in the coefficient of thermal expansion of the membrane. For this reason, when assembled in a case (Glass Tech Case), during reliability tests such as moisture resistance tests or bias tests, defects may occur in thin or cracked areas of the Bashiba 7 horn membrane, which may deteriorate reliability. friend.

(発明の構成1作用、効果) 本発明の特徴はアルミニウム配線を形成し友後、シリコ
ン酸化膜系被膜形成用塗布液を塗布し焼成して前記アル
ミニウム配線の凹部及び段部にシリコン酸化膜系被膜を
形成してから、バクベーショ/膜を形成する事にある。
(Structure 1 of the invention) A feature of the present invention is that after forming an aluminum wiring, a coating solution for forming a silicon oxide film is applied and baked to form a silicon oxide film on the recesses and steps of the aluminum wiring. The process consists of forming a film and then forming a coating/film.

本発明の目的は前述の欠点をなくし高信頼性の半導体装
置を提供する事にある。つまり本発明によればアルミニ
ウム配線形成後にシリコン酸化膜系被膜を凹部及び段部
に形成するのでコノタクト孔部のアルミニウム配線の凹
部や端部が埋まシウェハー表面がなだらかになる。この
為バフベージ=17膜もカバレッジよく薄い部分も亀裂
が入る事もなく形成できる。
An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable semiconductor device. That is, according to the present invention, after the aluminum wiring is formed, a silicon oxide film-based film is formed in the recesses and steps, so that the recesses and ends of the aluminum wiring in the contact holes are filled, and the wafer surface becomes smooth. For this reason, a buff page = 17 film can be formed with good coverage and without cracking even in thin parts.

(実施例) 次に実施例について第2図(a)〜(C)を参照しなが
ら詳細に説明子る。
(Example) Next, an example will be explained in detail with reference to FIGS. 2(a) to (C).

まず第2図(alのように半導体基板11上に従来と同
様に素子分離領域、ゲートポリシリ電極等を形成しく図
示はしていない)コンタクト穴を開孔し、アルミニウム
配線14.15を形成する。
First, contact holes are opened in FIG. 2 (not shown since element isolation regions, gate polysilicon electrodes, etc. are formed on the semiconductor substrate 11 in the same manner as in the prior art), and aluminum interconnections 14 and 15 are formed.

次に第2図(blのようにシリコン酸化膜系被膜形成用
塗布液t−塗布する。しかる後に300℃〜500℃の
温度でN2雰囲気中で焼成してシリコン酸化膜系被膜1
6を形成する。シリコン酸化膜系被膜形成用塗布液は粘
度が低い為コンタクト開孔部のアルミニウム配線14の
凹部やアルミニウム配線15の端部はシリコン酸化膜系
被膜形成用塗布液で埋められる。ここで焼成する事によ
ジ酸化膜系被膜16となる。この段階でウエノ1−表面
は段部や凹部が酸化膜系被膜16で埋められている為な
だらかになる。この後第2図(C)のようにバシベー7
117膜17を成長する。バシベーシ!/膜17は例え
ば醸化膜、窒化膜、リンガラス層膜、あるいはこれらの
組み合わせが用いられている。パシベーシ言ン膜17は
ウニノー−表面がなだらかな為カバレッジよく被着する
。従って極端に薄い部分が生じる事もなく、又亀裂も生
じない。
Next, as shown in FIG. 2 (bl), apply a coating solution t for forming a silicon oxide film. After that, it is baked in a N2 atmosphere at a temperature of 300°C to 500°C to form a silicon oxide film 1.
form 6. Since the coating liquid for forming a silicon oxide film has a low viscosity, the recesses of the aluminum wiring 14 and the ends of the aluminum wiring 15 in the contact openings are filled with the coating liquid for forming a silicon oxide film. By firing here, a dioxide film-based film 16 is formed. At this stage, the surface of the wafer 1 becomes smooth because the steps and depressions are filled with the oxide film 16. After this, as shown in Figure 2 (C),
117 film 17 is grown. Bashibeshi! The film 17 is, for example, a fermented film, a nitride film, a phosphor glass layer film, or a combination thereof. Since the passivation film 17 has a smooth surface, it can be deposited with good coverage. Therefore, there will be no extremely thin portions, and no cracks will occur.

以上詳細に説明し九ように本発明によればアルミニウム
配線を形成しシリコン酸化膜系被膜で凹部及び段部を埋
め九後バシペーシ!/膜を形成する事によυバゾベーシ
ッノ膜をカバレッジよく被着出来、亀裂も出来ないパシ
ベーション膜を形成でき、高信頼性の半導体装置を実現
出来る。
As described above in detail, according to the present invention, aluminum wiring is formed and the recesses and steps are filled with a silicon oxide film. By forming a / film, it is possible to deposit the υvazobasic film with good coverage, and a passivation film that does not form cracks can be formed, making it possible to realize a highly reliable semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来法を示す断面図である。第2図は本発明に
よる実施例を示す断面図である。 1.11・・・・・・半導体基板、2.12・・・・・
・拡散層、3.13・・・・・・絶縁膜、4,5.14
.15・・・・・・アルミニウム配線、6,17・・・
・・・パシベーション膜、16・・・・・・シリコン酸
化膜系被膜。 為    、
FIG. 1 is a sectional view showing a conventional method. FIG. 2 is a sectional view showing an embodiment according to the present invention. 1.11... Semiconductor substrate, 2.12...
・Diffusion layer, 3.13...Insulating film, 4,5.14
.. 15... Aluminum wiring, 6,17...
...Passivation film, 16...Silicon oxide film-based film. For the sake of,

Claims (2)

【特許請求の範囲】[Claims] (1)アルミニウム配線を形成する工程と、シリコン酸
化膜系被膜形成用塗布液を塗布し焼成して前記アルミニ
ウム配線の凹部及び段部にシリコン酸化膜系被膜を形成
する工程と、絶縁膜を成長する工程とを含む事を特徴と
する半導体装置の製造方法。
(1) A step of forming an aluminum wiring, a step of applying a coating liquid for forming a silicon oxide film and baking it to form a silicon oxide film in the recesses and steps of the aluminum wiring, and growing an insulating film. A method for manufacturing a semiconductor device, comprising the steps of:
(2)上記絶縁膜が酸化膜あるいはリンガラス層膜ある
いは窒化膜あるいは酸化膜、リンガラス層膜、窒化膜の
組み合わせである事を特徴とする特許請求の範囲第(1
)項記載の半導体装置の製造方法。
(2) Claim 1, wherein the insulating film is an oxide film, a phosphorus glass layer film, a nitride film, or a combination of an oxide film, a phosphorus glass layer film, and a nitride film.
) The method for manufacturing a semiconductor device according to item 2.
JP25665184A 1984-12-05 1984-12-05 Manufacture of semiconductor device Pending JPS61134038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25665184A JPS61134038A (en) 1984-12-05 1984-12-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25665184A JPS61134038A (en) 1984-12-05 1984-12-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61134038A true JPS61134038A (en) 1986-06-21

Family

ID=17295571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25665184A Pending JPS61134038A (en) 1984-12-05 1984-12-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61134038A (en)

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