JPH05121406A - Flattening of semiconductor - Google Patents

Abstract

PURPOSE:To maintain an excellent flatness and to prevent cracking when baking at high temperature. CONSTITUTION:An organic coating glass 4 is applied thick on the surface of a silicon substrate 1. Then, it is baked and removed by etching except for the portion between gate electrodes 2 on the silicon substrate 1. Then, the organic coating glass 4 is baked at a temperature higher than the previous baking process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor flattening method for flattening the surface of a silicon substrate after forming electrodes.

[0002]

2. Description of the Related Art Conventionally, a flattening method has been widely used in which an inorganic coating glass is applied to the electrode forming surface of a semiconductor so as to cover the convex portions of the electrode and make the electrode forming surface flat. As a result, the reliability of the wiring layer that electrically connects the electrodes is improved. That is, if the electrode formation surface is not flat, the wiring layer is often broken at the stepped portion of the uneven portion.

[0003]

By the way, with the inorganic coating glass, it is not possible to form a thick film that sufficiently covers the convex portion of the electrode. Therefore, in the application of the inorganic coating glass,
There is a problem that the flatness of the electrode formation surface is not good.
In addition, although it is possible to form a thick film with organic coated glass,
If a thick film is formed more than necessary, there arises a problem that cracks occur during the high temperature baking process in the next step. The present invention has been devised in view of the above problems,
An object of the invention is to provide a method of flattening a semiconductor which maintains good flatness and prevents cracks from being generated during high temperature baking.

[0004]

In order to solve the above problems, the present invention provides a semiconductor flattening method for flattening an electrode formation surface of a silicon substrate in a manufacturing process of a semiconductor integrated circuit. The organic coating glass is thickly applied to the insulating film laminated on the formation surface, the organic coating glass is baked by baking treatment, and the organic coating glass other than the portion between the electrodes is removed by etching, and the electrode is formed. It is characterized in that the organic coating glass applied in between is baked at a temperature higher than the baking temperature of the baking treatment.

[0005]

According to the above-mentioned structure, the coated glass thickly applied to the surface of the semiconductor integrated circuit is removed by etching after the baking process, except for the portion necessary for maintaining the flatness of the surface.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a main part of a semiconductor to which a method for planarizing a semiconductor according to the present invention is applied. In this figure, 1 is a silicon substrate. Reference numeral 2 is a gate electrode, which is formed on a silicon substrate using polysilicon or a refractory metal. Reference numeral 3 denotes an insulating film, which is formed by a CVD method such as a plasma CVD method on the silicon substrate 1 and the gate electrode 2.
Is laminated on the surface of. As shown in this figure, the insulating film 3
Has a concavo-convex portion because it is uniformly laminated along the surfaces of the silicon substrate 1 and the gate electrode 2. Reference numeral 4 denotes an organic coating glass, which is filled in the concave portion of the insulating film 3 and is formed so as to flatten the concave portion. Reference numeral 5 denotes a first-layer aluminum wiring, which is formed on the surface flattened by the organic coating glass 4 to electrically connect electrodes (not shown). Further, a plurality of layers of aluminum wirings are formed on the upper surface of the first-layer aluminum wirings 5 via insulating films (not shown).

Next, a method of planarizing the semiconductor according to the above-described embodiment will be described. 2 to 5 are cross-sectional views for explaining the method of planarizing the semiconductor. First, as shown in FIG. 2, a plurality of gate electrodes 2 are formed on the silicon substrate 1, and further, as shown in FIG. 3, an insulating film 3 is formed on the surfaces of the silicon substrate 1 and the gate electrode 2. ..

Next, as shown in FIG. 4, an organic coating 4 glass is thickly coated on the insulating film 3 to completely cover the surface. After thick coating, annealing (annealing) is performed at about 400 to 450 degrees Celsius to cure the organic coating glass 4. Here, the reason why the organic coating glass 4 is not baked (fired) at a temperature of 700 ° C. or higher is to prevent the occurrence of cracks.

Then, as shown in FIG. 5, the surface of the organic coating glass 4 is etched until sufficient flatness is maintained and the surface of the insulating film 3 is exposed.
As a result, the organic coating glass 4 is removed except for the portion filled in the concave portion of the insulating film 3. After removing the organic coating glass 4, a baking treatment is performed at 700 ° C. or higher to completely cure the organic coating glass 4. By the method described above, the surface on the silicon substrate 1 is flattened despite the uneven portion of the gate electrode 2. Then, after baking, a contact hole is formed by a known method, and further, a first layer aluminum wiring is formed to manufacture a semiconductor as shown in FIG.

Although the first-layer aluminum wiring 5 is formed after the baking treatment in the above-described embodiment, the insulating film 6 may be newly formed on the surface flattened by the organic coating glass 4. .. FIG. 6 is a cross-sectional view showing the semiconductor main part at this time. As a result, the insulation characteristics between the first-layer aluminum wiring 5 and the gate electrode 2 can be improved as compared with the embodiment shown in FIG. Further, it becomes easy to form the taper of the contact hole, the step coverage of the wiring is improved, and the electrical connection is ensured.

[0011]

According to the above-mentioned constitution, the present invention can realize the formation of a coated glass film which maintains good flatness and prevents cracks from being generated during high temperature baking. Further, since the coated glass film is removed except for the necessary amount, it is possible to prevent peeling or cracking of the coated glass film due to stress generation based on the difference in thermal expansion coefficient between the coated glass film and the insulating film, There is also an effect that disconnection of the first layer aluminum wiring and deterioration of the insulating layer are eliminated, and the reliability of the semiconductor is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a semiconductor to which a coated glass film forming method according to the present invention is applied.

FIG. 2 is a cross-sectional view for explaining a method for forming a coated glass film.

FIG. 3 is a cross-sectional view for explaining a method for forming a coated glass film.

FIG. 4 is a cross-sectional view for explaining a method for forming a coated glass film.

FIG. 5 is a cross-sectional view for explaining a method for forming a coated glass film.

FIG. 6 is a cross-sectional view showing a main part of a semiconductor having improved insulation characteristics in an example.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Gate electrode, 3, 6 ... Insulating film, 4 ... Organic coating glass, 5 ... First layer aluminum wiring

Claims (1)

[Claims] 1. A method for flattening a semiconductor substrate in which a surface of a silicon substrate on which electrodes are formed is flattened in a manufacturing process of a semiconductor integrated circuit, wherein an insulating film laminated on the surface of the silicon substrate on which electrodes are formed is coated with an organic coating glass. Then, the organic coating glass is baked by baking treatment, the organic coating glass other than the portion between the electrodes is removed by etching, and the organic coating glass coated between the electrodes is baked at the baking temperature. A method of planarizing a semiconductor, which comprises firing at a higher temperature than the above.