JPH0121626B2 - - Google Patents
Info
- Publication number
- JPH0121626B2 JPH0121626B2 JP62311980A JP31198087A JPH0121626B2 JP H0121626 B2 JPH0121626 B2 JP H0121626B2 JP 62311980 A JP62311980 A JP 62311980A JP 31198087 A JP31198087 A JP 31198087A JP H0121626 B2 JPH0121626 B2 JP H0121626B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- glass layer
- film
- sog
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011521 glass Substances 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置における多層配線の形成
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming multilayer wiring in a semiconductor device.
多層配線半導体装置においては、第１図を参照
し半導体基板１表面に第１層Al配線２を形成し、
この上に層間絶縁膜としてSOG（スピン・オン・
グラス）と称する粉末SiO2の粘稠溶液体を塗布
し焼き付けた第１のガラス層３とCVD（気相化学
反応堆積）法によるPSG（リン・シリケート・ガ
ラス）からなる第２のガラス層４とを積層形成
し、その上に第２層Al配線６を形成した構造が
従来より採用されている。このような多層配線で
は層間絶縁膜表面の凹凸を極力少なくするために
は、回転塗布により形成するSOG膜３をなるべ
く厚くする必要がある。ところがSOG膜厚が
1000Å以上になると第１層Al配線の熱的マイグ
レーシヨンにより生ずるヒロツクスと称する異常
突起５によつてSOG膜にクラツクを発生し易い。
このクラツクのために層間耐圧が低下し、外観的
にも不良状態となつた。 In a multilayer wiring semiconductor device, referring to FIG. 1, a first layer Al wiring 2 is formed on the surface of a semiconductor substrate 1,
On top of this, SOG (spin-on) is applied as an interlayer insulating film.
A first glass layer 3 made of a viscous solution of powdered SiO 2 called glass and baked, and a second glass layer 4 made of PSG (phosphorus silicate glass) by CVD (vapor phase chemical deposition) method. Conventionally, a structure has been adopted in which a second layer Al wiring 6 is formed on top of the two layers. In such a multilayer wiring, in order to minimize the unevenness on the surface of the interlayer insulating film, it is necessary to make the SOG film 3 formed by spin coating as thick as possible. However, the SOG film thickness
When the thickness exceeds 1000 Å, cracks are likely to occur in the SOG film due to abnormal protrusions 5 called hillocks caused by thermal migration of the first layer Al wiring.
This crack lowered the interlayer breakdown voltage and resulted in a poor appearance.
本発明は上記した従来技術の欠点を除くために
なされたものであり、その一つの目的はAlにお
けるヒロツクスを押えることであり、他の目的は
SOG膜厚を大きくしてもクラツクの発生しない
層間絶縁膜の提供にある。 The present invention was made to eliminate the above-mentioned drawbacks of the prior art, and one purpose is to suppress the hillocks in Al, and the other purpose is to suppress the hillocks in Al.
An object of the present invention is to provide an interlayer insulating film that does not cause cracks even when the SOG film thickness is increased.
上記目的を達成するために、本発明は基板上に
形成したアルミニウム配線上にシリコンを含む溶
液を塗布し、かつ焼付けすることによつて第１の
ガラス層を形成し、前記第１のガラス層に重ねて
第２のガラス層をデポジシヨンした後、前記第２
のガラス層上に延在する他の配線を形成する多層
配線形成法において、前記第１のガラス層の形成
前に、前記アルミニウム配線の上面および側面、
ならびに前記アルミニウム配線が形成されなかつ
た前記基板表面を覆つて、前記第１のガラス層よ
りも硬質の絶縁膜をプラズマ放電を利用した気相
からのデポジシヨンにより形成し、この絶縁膜上
に、前記第１のガラス層を形成することを特徴と
する。 In order to achieve the above object, the present invention forms a first glass layer by applying a silicon-containing solution on an aluminum wiring formed on a substrate and baking it, and the first glass layer After depositing a second layer of glass over the
In the multilayer wiring formation method for forming another wiring extending on the glass layer, before forming the first glass layer, the upper surface and side surface of the aluminum wiring,
Further, an insulating film harder than the first glass layer is formed by vapor phase deposition using plasma discharge to cover the surface of the substrate on which the aluminum wiring is not formed, and on this insulating film, the It is characterized by forming a first glass layer.
以下、本発明を実施例にそつて説明する。 The present invention will be explained below with reference to Examples.
第２図において、基板１上に第１のAl配線２
を形成し、この上にプラズマ放電を利用し300℃
で気相よりデポジシヨンしたSi3N4（シリコン窒
化物）による窒化膜７（プラズマナイトライド膜
と称す）とを膜厚1500〜2000Åに形成し、次い
で、SiO2粉末を溶剤により溶いた粘稠溶液体を
回転塗布して焼付けたSOG膜３を膜厚2000〜
3000Åに形成し、さらにリンを含むSiO2をデポ
ジシヨンして膜厚4000〜6000ÅのPSG膜４を形
成する。このPSG膜の上に第２のAl配線を形成
することで多層配線を実現する。 In FIG. 2, a first Al wiring 2 is placed on a substrate 1.
300℃ using plasma discharge on top of this
A nitride film 7 (referred to as plasma nitride film) of Si 3 N 4 (silicon nitride) deposited from the gas phase was formed to a thickness of 1500 to 2000 Å, and then a viscous film made by dissolving SiO 2 powder in a solvent was formed. The SOG film 3 is made by spin-coating the solution and baking it to a film thickness of 2000~
A PSG film 4 having a thickness of 4000 to 6000 Å is formed by depositing SiO 2 containing phosphorus. A multilayer wiring is realized by forming a second Al wiring on this PSG film.
以上実施例で述べた本発明によれば、第１の
Al配線の上に形成したＰ―Si3N4はそれ自体SOG
に比して硬質でありAl配線表面に強固に接合し
Al表面にヒロツクスが生じることを防止する。
したがつてSOG膜厚を厚くしてもクラツクが発
生しなくなり、層間耐圧を高めることができる。
また、SOG、PSG、第２層アルミニウムのデポ
ジシヨン工程以降の製造工程における熱履歴によ
つて第１層アルミニウムのグレイン（Grain）が
動き層間クラツクが発生するのを防ぐこともでき
る。すなわち、第１層アルミニウムの表面を包む
ように、低温でCVD処理ができるプラズマ放電
によつて、SOGより硬質な膜が予め被着される
ので、SOGの被着、PSGの被着および第２層ア
ルミニウムの被着工程における熱処理において第
１層アルミニウム層の表面に発生するかもしれな
いアルミニウムの突起（ヒロツクス）を防止する
ことができる。 According to the present invention described in the embodiments above, the first
P-Si 3 N 4 formed on Al wiring is itself SOG
It is hard compared to the aluminum wiring and can be firmly bonded to the surface of the Al wiring.
Prevents hillocks from forming on the Al surface.
Therefore, even if the SOG film thickness is increased, cracks do not occur, and the interlayer breakdown voltage can be increased.
Furthermore, it is also possible to prevent the grains of the first layer aluminum from moving due to thermal history in the manufacturing process after the deposition process of SOG, PSG, and second layer aluminum, and causing interlayer cracks. In other words, a film that is harder than SOG is coated in advance by plasma discharge, which can be performed at low temperatures by CVD, so that it wraps around the surface of the first layer of aluminum, so that the SOG, PSG, and second layers are coated in advance. It is possible to prevent aluminum protrusions (hillocks) that may occur on the surface of the first aluminum layer during heat treatment in the aluminum deposition process.
なお、上記実施例では膜厚、処理温度等を固定
したが、これらの値は設計によつて任意に変更で
きる。 In the above embodiments, the film thickness, processing temperature, etc. are fixed, but these values can be changed arbitrarily depending on the design.
本発明によれば下記のような諸効果がもたらさ
れる。(1)SOG膜厚を厚くしてウエハ表面の大幅
な平坦化が可能となつた。(2)SOGと第１のAl配
線が接触しないためAl線の腐食防止ができる。
(3)第３図を参照し第1Al配線２上の層間絶縁膜３
にスルーホール８をエツチングする場合に従来の
２層配線では基板のオーバエツチとともにAl配
線の側面がサイドエツチ（点線９で示す）された
が、本発明によれば、Si3N4膜７があるためにか
かる必要はない。(4)パターン誤差のためにSOG、
PSGの再生（つけ直し）は従来は不可能であつ
たがこれが可能となつた。(5)SOG、PSGのクラ
ツク防止、ヒロツクスによるAl層間の短絡を防
止できる。(6)SOGのクラツクをなくせるため外
観不良がなくなる。 According to the present invention, the following effects are brought about. (1) By increasing the SOG film thickness, it has become possible to significantly flatten the wafer surface. (2) Since the SOG and the first Al wiring do not come into contact, corrosion of the Al wire can be prevented.
(3) Referring to Figure 3, the interlayer insulating film 3 on the first Al wiring 2
When etching the through hole 8 in the conventional two-layer wiring, the side surface of the Al wiring was side-etched (indicated by dotted line 9) along with over-etching of the substrate, but according to the present invention, because of the Si 3 N 4 film 7, There is no need to go through the process. (4) SOG due to pattern error;
Previously it was impossible to regenerate (reinstall) PSG, but now it is possible. (5) Prevents cracks in SOG and PSG, and short circuits between Al layers due to heroes. (6) SOG cracks can be eliminated, eliminating appearance defects.
また、本発明によれば、硬質で、かつ緻密なプ
ラズマ放電による膜が第１層のAl配線を包囲す
るので、Al配線を基板に強固に固定するように
作用する。このため、Al配線が熱的影響によつ
て膨張、収縮したとしても、比較的に柔らかく、
脆いSOG膜は損傷されることがない。さらに、
SOGとプラズマ処理絶縁膜との密着性が良くな
る。 Further, according to the present invention, since the hard and dense film produced by plasma discharge surrounds the first layer Al wiring, it acts to firmly fix the Al wiring to the substrate. Therefore, even if the Al wiring expands or contracts due to thermal effects, it remains relatively soft.
The fragile SOG film will not be damaged. moreover,
The adhesion between SOG and the plasma-treated insulating film is improved.
本発明は、特に、第１のAl配線、SOG膜、お
よびPSG膜の３者を組合わせた構造に適用して
有効であり、そのSOG膜によつて、Al配線の段
差部が埋込まれるので、SOG膜上にPSG膜を均
一に厚くデポジシヨンすることができる。 The present invention is particularly effective when applied to a structure in which the first Al wiring, an SOG film, and a PSG film are combined, and the stepped portion of the Al wiring is buried by the SOG film. Therefore, the PSG film can be deposited uniformly and thickly on the SOG film.
本発明は多層のAl配線間の層間絶縁膜に全て
適用できる。 The present invention can be applied to all interlayer insulating films between multilayer Al interconnects.
第１図は従来の２層配線の例を示す断面図、第
２図は本発明による２層配線の例を示す断面図、
第３図は本発明による多層配線で総間絶縁膜にス
ルーホールを設けた場合の例を示す断面図であ
る。
１…基板、２…第１層のAl配線、３…SOG膜、
４…PSG膜、５…ヒロツクス、６…第２層のAl
配線、７…Si3N4膜、８…スルーホール。
FIG. 1 is a sectional view showing an example of conventional two-layer wiring, FIG. 2 is a sectional view showing an example of two-layer wiring according to the present invention,
FIG. 3 is a cross-sectional view showing an example of a multilayer wiring according to the present invention in which through holes are provided in the interlayer insulating film. 1...Substrate, 2...First layer Al wiring, 3...SOG film,
4...PSG film, 5...Hirox, 6...2nd layer Al
Wiring, 7...Si 3 N 4 film, 8... Through hole.
Claims (1)
コンを含む溶液を塗布し、かつ焼付けすることに
よつて第１のガラス層を形成し、前記第１のガラ
ス層に重ねて第２のガラス層をデポジシヨンした
後、前記第２のガラス層上に延在する他の配線を
形成する多層配線形成法において、前記第１のガ
ラス層の形成前に、前記アルミニウム配線の上面
および側面、ならびに前記アルミニウム配線が形
成されなかつた前記基板表面を覆つて、前記第１
のガラス層よりも硬質の絶縁膜をプラズマ放電を
利用した気相からのデポジシヨンにより形成し、
この絶縁膜上に、前記第１のガラス層を形成する
ことを特徴とする多層配線形成法。 ２ 前記絶縁膜は、プラズマ放電を利用した気相
からのデポジシヨンにより、前記アルミニウム配
線の上面および側面に均一の厚さに形成されるこ
とを特徴とする特許請求の範囲第１項記載の多層
配線形成法。[Claims] 1. A first glass layer is formed by applying a silicon-containing solution onto an aluminum wiring formed on a substrate and baking it, and a first glass layer is formed on the first glass layer. In the multilayer wiring forming method, in which another wiring extending on the second glass layer is formed after depositing a second glass layer, the top and side surfaces of the aluminum wiring are formed before forming the first glass layer. , and covering the surface of the substrate on which the aluminum wiring is not formed, the first
An insulating film that is harder than the glass layer is formed by vapor phase deposition using plasma discharge.
A method for forming multilayer wiring, comprising forming the first glass layer on the insulating film. 2. The multilayer wiring according to claim 1, wherein the insulating film is formed to have a uniform thickness on the top and side surfaces of the aluminum wiring by vapor phase deposition using plasma discharge. Formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31198087A JPS63158853A (en) | 1987-12-11 | 1987-12-11 | Method of forming multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31198087A JPS63158853A (en) | 1987-12-11 | 1987-12-11 | Method of forming multilayer interconnection |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10912379A Division JPS5633899A (en) | 1979-08-29 | 1979-08-29 | Method of forming multilayer wire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63158853A JPS63158853A (en) | 1988-07-01 |
| JPH0121626B2 true JPH0121626B2 (en) | 1989-04-21 |
Family
ID=18023753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31198087A Granted JPS63158853A (en) | 1987-12-11 | 1987-12-11 | Method of forming multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63158853A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100314806B1 (en) | 1998-10-29 | 2002-02-19 | 박종섭 | Method for forming spin on glass layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133575A (en) * | 1974-09-17 | 1976-03-22 | Nippon Telegraph & Telephone | TASOHAISENKOZO |
| JPS5214365A (en) * | 1975-07-25 | 1977-02-03 | Hitachi Ltd | Process for formation of insulating membrane by spreading |
-
1987
- 1987-12-11 JP JP31198087A patent/JPS63158853A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133575A (en) * | 1974-09-17 | 1976-03-22 | Nippon Telegraph & Telephone | TASOHAISENKOZO |
| JPS5214365A (en) * | 1975-07-25 | 1977-02-03 | Hitachi Ltd | Process for formation of insulating membrane by spreading |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63158853A (en) | 1988-07-01 |
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