JPS61131856U - - Google Patents

Info

Publication number
JPS61131856U
JPS61131856U JP1985014121U JP1412185U JPS61131856U JP S61131856 U JPS61131856 U JP S61131856U JP 1985014121 U JP1985014121 U JP 1985014121U JP 1412185 U JP1412185 U JP 1412185U JP S61131856 U JPS61131856 U JP S61131856U
Authority
JP
Japan
Prior art keywords
diffusion region
electrode
lead wire
semiconductor substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985014121U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985014121U priority Critical patent/JPS61131856U/ja
Publication of JPS61131856U publication Critical patent/JPS61131856U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案による可変容量ダイオードの断
面図、第２図は従来の可変容量ダイオードの断面
図である。 主な図番の説明、１は可変容量ダイオード、２
はＮ＋型のシリコン基板、３はＮ型のエピタキシ
ヤル層、４はリング状のＰ＋型の拡散領域、５は
薄いＰ＋型の拡散領域、６は第１の絶縁膜、７は
第２の絶縁膜、８は電極、９はリード線、１０は
ジヤケツトコート膜である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 一導電型の半導体基板と該半導体基板に形成し
    た逆導電型の拡散領域と該拡散領域上に形成した
    電極と該電極上に形成したリード線とを具備し空
    乏層の厚さを容量変化として検知する可変容量ダ
    イオードに於て、前記拡散領域上であり前記リー
    ド線接合部と対応する前記電極内に絶縁膜を具備
    することを特徴とした可変容量ダイオード。
JP1985014121U 1985-02-01 1985-02-01 Pending JPS61131856U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985014121U JPS61131856U (ja) 1985-02-01 1985-02-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985014121U JPS61131856U (ja) 1985-02-01 1985-02-01

Publications (1)

Publication Number Publication Date
JPS61131856U true JPS61131856U (ja) 1986-08-18

Family

ID=30498755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985014121U Pending JPS61131856U (ja) 1985-02-01 1985-02-01

Country Status (1)

Country Link
JP (1) JPS61131856U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014232883A (ja) * 2014-07-28 2014-12-11 ローム株式会社 バイポーラ型半導体装置
US11824014B2 (en) 2020-03-30 2023-11-21 Mitsubishi Electric Corporation Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014232883A (ja) * 2014-07-28 2014-12-11 ローム株式会社 バイポーラ型半導体装置
US11824014B2 (en) 2020-03-30 2023-11-21 Mitsubishi Electric Corporation Semiconductor device

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