JPS61131481A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS61131481A JPS61131481A JP25157084A JP25157084A JPS61131481A JP S61131481 A JPS61131481 A JP S61131481A JP 25157084 A JP25157084 A JP 25157084A JP 25157084 A JP25157084 A JP 25157084A JP S61131481 A JPS61131481 A JP S61131481A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- source
- thin film
- film transistor
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 239000000460 chlorine Substances 0.000 claims 1
- 229910052801 chlorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 238000010276 construction Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000002178 crystalline material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜トランジスタ(TPT)に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor (TPT).
従来のこの種の薄膜トランジスタはそれぞれほぼ長方形
のゲート電極、ソース電極およびドレイン電極がそれぞ
れ平行に配置されている。このような従来の薄膜トラン
ジスタにおいて、ソース−ドレイン電流を増減させるに
はチャネル幅、すなわちゲート電極、ソース電極および
ドレイン電極の長さを増減させる方法が採用されている
1例えば、チャネル長l10A1.チャネル幅500t
mを有する代表的薄膜トランジスタのソース−ドレイン
電流は約10μAである。したがって、100μAの大
きなソース−ドレイン電流が必要な場合は、チャネル幅
は約5.lWnと長くなっ・てしまう。Conventional thin film transistors of this type each have substantially rectangular gate electrodes, source electrodes, and drain electrodes arranged in parallel. In such conventional thin film transistors, a method is adopted to increase or decrease the source-drain current by increasing or decreasing the channel width, that is, the lengths of the gate electrode, source electrode, and drain electrode. Channel width 500t
The source-drain current of a typical thin film transistor with m is about 10 μA. Therefore, if a large source-drain current of 100 μA is required, the channel width should be approximately 5.5 μA. It ends up being as long as lWn.
一方、結晶性材料を基板に用いた電界効果型トランジス
タにおいては、ソ、−スートレイン電流を増大させるた
めに、電極をくし形、正張波状にするなどの工夫がなさ
れている。(文献不詳)【発明が解決しようとする問題
点〕
前述のように、 100μAのソース−ドレイン電流を
得るためには、チャネル長を10.としまた場合。On the other hand, in a field effect transistor using a crystalline material as a substrate, in order to increase the soustrain current, devises have been made such as making the electrodes comb-shaped or vertically wave-shaped. (Reference unknown) [Problem to be solved by the invention] As mentioned above, in order to obtain a source-drain current of 100 μA, the channel length must be set to 10. Toshimata case.
チャネル幅は約5.INと非常に長くなってしまう。The channel width is approximately 5. IN becomes very long.
このようにチャネル幅もしくはチャネル長が一方向に長
くなると、素子の設計の余裕度が狭くなり、用途も狭く
限定されてしまうという問題が生ずる。When the channel width or channel length increases in one direction as described above, there arises a problem that the margin for element design becomes narrower and the applications are also narrowly limited.
また、結晶性材料を基板に用いた電界効果型トランジス
タにおいて、電極をくし形あるいは正張波状にする等の
工夫がなされたものでは、三つの電極が同一平面状にあ
る(コプラナー型)ため、(i)高密度に電極を配置す
ることができない。In addition, in field effect transistors using crystalline materials as substrates, in which the electrodes are designed to have a comb shape or a straight wave shape, the three electrodes are on the same plane (coplanar type). (i) Electrodes cannot be arranged in high density.
(…)現在の微細加工の技術では、電極間の距離を充分
小さくすることができず、電極間の距離が大きくなって
キャリヤの移動度の小さな半導体薄膜を用いることがで
きないという問題がある。(...) Current microfabrication techniques have the problem that the distance between the electrodes cannot be made sufficiently small, and the distance between the electrodes becomes large, making it impossible to use a semiconductor thin film with low carrier mobility.
上述した従来技術の問題点を解決するために、本発明の
薄膜トランジスタは、ゲート電極を、半導体層を介して
ソース電極およびドレイン電極に向かい合うように配置
し、かつソース電極およびドレイン電極のうちいずれか
一方の電極がほぼ同一平面上で他方の電”極を取り囲−
むように配置したものである。あるいはさらに、ソース
電極およびドレイン電極に複数の枝を持たせる。このよ
うな構成により、本発明はチャネル幅もしくはチャネル
長(つまり電極の長さ)を一方向に長くすることなく、
基板面積を有効に利用し高密度化を達成するものである
。In order to solve the problems of the prior art described above, the thin film transistor of the present invention has a gate electrode arranged to face a source electrode and a drain electrode with a semiconductor layer interposed therebetween, and one of the source electrode and the drain electrode. One electrode surrounds the other on almost the same plane.
It is arranged so that Alternatively, the source electrode and the drain electrode may have multiple branches. With such a configuration, the present invention can be used without increasing the channel width or channel length (that is, the length of the electrode) in one direction.
This effectively utilizes the substrate area and achieves high density.
実施例 1
第1図(5k)は本発明の実施例の薄膜トランジスタの
平面図、第1図(b)は第1図(a)のC−D断面図で
ある。これらの図に示した薄膜トランジ・スタを作製し
た。Example 1 FIG. 1(5k) is a plan view of a thin film transistor according to an example of the present invention, and FIG. 1(b) is a sectional view taken along line CD in FIG. 1(a). The thin film transistors shown in these figures were fabricated.
すなわち、まずガラス基板ll上にCr電極(ゲート電
極)12を真空中で電子ビーム蒸着法により形成した。That is, first, a Cr electrode (gate electrode) 12 was formed on a glass substrate 11 in vacuum by electron beam evaporation.
次に、その上に膜厚0.3−の窒化シリコン層(ゲート
絶縁層)13をプラズマCVD法により形成した。この
とき用いた反応ガスは、SiH,とNH,とN2との混
合ガス(圧力0.5〜I Torr)であった。Next, a silicon nitride layer (gate insulating layer) 13 having a film thickness of 0.3 mm was formed thereon by plasma CVD. The reaction gas used at this time was a mixed gas of SiH, NH, and N2 (pressure 0.5 to I Torr).
さらに、その上に膜厚0.3#IIの非晶質水素化シリ
コン層(半導体層)14をプラズマCVD法により形成
した。このとき用いた反応ガスは、SiH。Furthermore, an amorphous hydrogenated silicon layer (semiconductor layer) 14 having a film thickness of 0.3#II was formed thereon by plasma CVD. The reaction gas used at this time was SiH.
とH2との混合ガス(圧力0.5〜I Torr)であ
った。and H2 (pressure 0.5 to I Torr).
なお、本実施例では、この半導体層14としてシリコン
を主成分とし、水素を含有する非晶質水素化シリコンを
用いたが、シリコンもしくはゲルマニウムなどを主成分
とし、水素の他、フッ素、塩素、炭素、窒素、酸素など
を含む膜を採用することができる。もちろん、これに限
定されることはない。In this embodiment, amorphous hydrogenated silicon containing silicon and hydrogen as the main component was used as the semiconductor layer 14. A film containing carbon, nitrogen, oxygen, etc. can be used. Of course, it is not limited to this.
最後唄、この上にCr電極(ソース電極15およびドレ
イン電極16)を電子ビーム蒸着法により形成した。な
お、チャネル長は10.、チャネル幅は5腫とした。On the final song, Cr electrodes (source electrode 15 and drain electrode 16) were formed by electron beam evaporation. Note that the channel length is 10. , the channel width was 5 mm.
本実施例の薄膜トランジスタは1図示のように。The thin film transistor of this example is as shown in Figure 1.
ゲート電極12が半導体層14を介してソース電極15
およびドレイン電極16に向かい合って配置してあり、
かつ弧状に形成されたソース電極15が同じくそれより
も半径の小さい弧状に形成されたドレイン電極16を同
一平面上で取り囲むように配置しである。The gate electrode 12 connects to the source electrode 15 via the semiconductor layer 14.
and are arranged facing the drain electrode 16,
A source electrode 15 formed in an arc shape is arranged so as to surround a drain electrode 16, which is also formed in an arc shape with a smaller radius, on the same plane.
このような構成になっているので、100μAのソース
−ドレイン電流を得ることができる10−の、チャネル
長および5■のチャネル幅を有する薄膜トランジスタを
直径約1.9閣内に収めることができ、従来同じソース
−ドレイン電流を得るために同じチャネル長でチャネル
幅の方向に約5.1−の長さが必要であった薄膜トラン
ジスタに比べて約173に長さを縮小することができた
。さらに、ゲート電極、12、ソース電極15.ドレイ
ン電極16が図示のごとくいずれも線状に形成されてい
るので、電流のリークおよびショートを防止し得る。With this configuration, a thin film transistor with a channel length of 10 mm and a channel width of 5 mm, which can obtain a source-drain current of 100 μA, can be housed within a diameter of approximately 1.9 mm, which is different from conventional Compared to a thin film transistor which requires a length of about 5.1 mm in the channel width direction for the same channel length to obtain the same source-drain current, the length can be reduced to about 173 mm. Furthermore, a gate electrode 12, a source electrode 15. Since the drain electrodes 16 are all formed in a linear shape as shown, current leakage and short circuit can be prevented.
実施例 2 ′
第2図(a)は本発明の別の実施例の薄膜トランジスタ
の平面図、第21m(b)は第2図(a)のE−F断面
図である。図示のような*mhランジスタを実施例1と
同様にして作製した。Embodiment 2' FIG. 2(a) is a plan view of a thin film transistor according to another embodiment of the present invention, and 21m(b) is a sectional view taken along line EF in FIG. 2(a). A *mh transistor as shown in the figure was produced in the same manner as in Example 1.
本実施例、の薄膜トランジスタも、ゲート電極(Cr電
極)22が半導体層24を介してソース電極25および
ドレイン電極26(C:rfft極)に向かい合って配
置してあり、かつソース電極25が同一平面上でドレイ
ン電極26を取り囲むように配置しである。さらに1本
実施例ではソース電極25およびドレイン電極26はそ
れぞれ複数の枝を有している。In the thin film transistor of this embodiment, the gate electrode (Cr electrode) 22 is arranged to face the source electrode 25 and the drain electrode 26 (C: rfft pole) via the semiconductor layer 24, and the source electrode 25 is on the same plane. It is arranged so as to surround the drain electrode 26 on the top. Furthermore, in this embodiment, the source electrode 25 and the drain electrode 26 each have a plurality of branches.
なお、ゲート絶縁層(窒化シリコン層)23と半導体層
(非晶質水素化シリコン層)24の膜厚はいずれも0.
3.とし、チャネル長は110l1.チャネル幅は5■
とした。 このような構成になっているので、100μ
Aのソース−ドレイン電流を得ることができる10−の
チャネル長、5購のチャネル幅を有する薄膜トランジス
タを縦横1.2+nの正方形内に収めることができ、従
来同じチャネル長でチャネル幅の方向に約5.1mの長
さが必要であったのに比べて約174に長さを縮小する
ことができた。Note that the film thicknesses of the gate insulating layer (silicon nitride layer) 23 and the semiconductor layer (amorphous hydrogenated silicon layer) 24 are both 0.
3. and the channel length is 110l1. Channel width is 5■
And so. With this configuration, 100μ
A thin film transistor with a channel length of 10 and a channel width of 5, which can obtain a source-drain current of A, can be housed within a square of 1.2+n in length and width. Compared to the required length of 5.1 m, the length could be reduced to approximately 174 m.
このように、本実施例では、電極を複数の枝状に分けた
ことにより、実施例1よりも基板に対する有効面積を大
きくすることができ、より大きいソース−ドレイン電流
を得ること−ができる。さらに。In this way, in this example, by dividing the electrode into a plurality of branches, the effective area relative to the substrate can be made larger than in Example 1, and a larger source-drain current can be obtained. moreover.
ゲート電極22、ソース電極25.ドレイン電極26が
図示のごとくいずれも線状に形成されているので。Gate electrode 22, source electrode 25. The drain electrodes 26 are all formed in a linear shape as shown in the figure.
電流のリークおよびショートを防止し得る。Current leakage and short circuits can be prevented.
上述のように、上記実施例1.2の薄膜トランジスタに
おいては、従来のごとくチャネル幅もしくはチャネル長
を一方向に長くしなくても大きなソース−ドレイン電流
を取り出すことができた。As described above, in the thin film transistor of Example 1.2, a large source-drain current could be extracted without increasing the channel width or channel length in one direction as in the conventional case.
また、ゲート電極を半導体層を介してソース電極および
ドレイン電極に向かい合うように配置しであるため、電
極間の距離を小さくすることができ、高密度に電極を配
置することができた。Further, since the gate electrode is arranged to face the source electrode and the drain electrode with the semiconductor layer in between, the distance between the electrodes can be reduced, and the electrodes can be arranged at high density.
な−お1本発明は上記の実施例に限定されることなく、
電極の形状など特許請求の範囲内においている・いろな
変形があり得ることはいうまで−tI?い、。Note that the present invention is not limited to the above embodiments,
It goes without saying that there may be various modifications such as the shape of the electrode within the scope of the claims. stomach,.
また、上記実施例ではゲート絶縁層を有する薄膜トラン
ジスタを示したが、ゲート絶縁層を有しないショットキ
ー型の薄膜トランジスタに適用してもよい、また、上記
実施例では、基板の上にゲート電極、その上にゲート絶
縁層、その上に半導体層、さらにその上にソース−ドレ
イン電極を順次積載した構造のものを示したが、基板の
上にソース−ドレイン電極!極、その上に半導体層、そ
の上にゲート絶縁膜、さらにその上にゲート電極を順次
積載した薄膜トランジスタに適用してもよい、さらに、
ゲート電極と、ソース−ドレイン電極とを半導体層を介
して重なり合わせてもよく、こうすればいっそう高密度
に電極を配置することができる。Further, although the above embodiment shows a thin film transistor having a gate insulating layer, it may also be applied to a Schottky type thin film transistor having no gate insulating layer. The structure shown above has a gate insulating layer on top, a semiconductor layer on top of that, and a source-drain electrode on top of that in order, but the source-drain electrodes are on top of the substrate! The present invention may be applied to a thin film transistor in which a pole, a semiconductor layer thereon, a gate insulating film thereon, and a gate electrode thereon are sequentially stacked;
The gate electrode and the source-drain electrode may be overlapped with each other with a semiconductor layer interposed therebetween, and in this case, the electrodes can be arranged with even higher density.
C発明の効果〕
以上説明したように、本発明は半導体層を介してソース
−ドレイン電極に向がい合うようにゲート電極を配置し
、かつソース電極とドレイン電極のうち一方が他方を取
り囲むように配置したことにより、素子の長さを縮小し
、電極を高密度に配置することができる。したがって、
素子設計の余裕度を向上させ、用途の範囲を広げること
ができる効果がある。C. Effects of the Invention] As explained above, the present invention provides a structure in which the gate electrode is arranged so as to face the source-drain electrode through the semiconductor layer, and one of the source electrode and the drain electrode surrounds the other. By arranging the electrodes, the length of the element can be reduced and the electrodes can be arranged with high density. therefore,
This has the effect of increasing the margin of element design and expanding the range of applications.
第1図(a)は本発明の実施例の薄膜トランジスタの平
面図、第1図(b)は第1図(a)の07、D断面図、
第、2図(a)は本発明の別の実施例。
の薄膜トランジスタの平fa11.第2図(b)は第2
図(a)のE−F断面図である。FIG. 1(a) is a plan view of a thin film transistor according to an embodiment of the present invention, FIG. 1(b) is a sectional view of 07, D in FIG. 1(a),
FIG. 2(a) shows another embodiment of the present invention. Thin film transistor flat fa11. Figure 2(b) shows the second
It is EF sectional drawing of figure (a).
Claims (3)
イン電極、半導体層を備えた薄膜トランジスタにおいて
、上記ゲート電極は上記半導体層を介して上記ソース電
極およびドレイン電極に向かい合うように配置され、か
つ該ソース電極およびドレイン電極のうちいずれか一方
の電極がほぼ同一平面上で他方の電極を取り囲むように
配置されていることを特徴とする薄膜トランジスタ。(1) In a thin film transistor including at least a substrate, a source electrode, a gate electrode, a drain electrode, and a semiconductor layer, the gate electrode is arranged to face the source electrode and the drain electrode with the semiconductor layer interposed therebetween, and the source electrode and a drain electrode, one of which is arranged so as to surround the other electrode on substantially the same plane.
とも一方が複数の枝状に分かれていることを特徴とする
特許請求の範囲第1項記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein at least one of the source electrode and the drain electrode is divided into a plurality of branches.
少なくとも一方を主成分とし、かつ水素、フッ素、塩素
、炭素、窒素、酸素の少なくとも一つを含むことを特徴
とする特許請求の範囲第1項記載の薄膜トランジスタ。(3) The semiconductor layer according to claim 1, wherein the semiconductor layer has at least one of silicon or germanium as a main component and contains at least one of hydrogen, fluorine, chlorine, carbon, nitrogen, and oxygen. Thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25157084A JPS61131481A (en) | 1984-11-30 | 1984-11-30 | Thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25157084A JPS61131481A (en) | 1984-11-30 | 1984-11-30 | Thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61131481A true JPS61131481A (en) | 1986-06-19 |
Family
ID=17224777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25157084A Pending JPS61131481A (en) | 1984-11-30 | 1984-11-30 | Thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61131481A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5057889A (en) * | 1987-07-06 | 1991-10-15 | Katsuhiko Yamada | Electronic device including thin film transistor |
JP2006091654A (en) * | 2004-09-27 | 2006-04-06 | Casio Comput Co Ltd | Pixel driving circuit and image display device |
US7688392B2 (en) | 2006-04-06 | 2010-03-30 | Chunghwa Picture Tubes, Ltd. | Pixel structure including a gate having an opening and an extension line between the data line and the source |
JP2014112687A (en) * | 2005-02-03 | 2014-06-19 | Semiconductor Energy Lab Co Ltd | Thin-film integrated circuit, module, and electronic apparatus |
-
1984
- 1984-11-30 JP JP25157084A patent/JPS61131481A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5057889A (en) * | 1987-07-06 | 1991-10-15 | Katsuhiko Yamada | Electronic device including thin film transistor |
JP2006091654A (en) * | 2004-09-27 | 2006-04-06 | Casio Comput Co Ltd | Pixel driving circuit and image display device |
JP4543315B2 (en) * | 2004-09-27 | 2010-09-15 | カシオ計算機株式会社 | Pixel drive circuit and image display device |
US7928932B2 (en) | 2004-09-27 | 2011-04-19 | Casio Computer Co., Ltd. | Display element drive circuit and display apparatus |
JP2014112687A (en) * | 2005-02-03 | 2014-06-19 | Semiconductor Energy Lab Co Ltd | Thin-film integrated circuit, module, and electronic apparatus |
US7688392B2 (en) | 2006-04-06 | 2010-03-30 | Chunghwa Picture Tubes, Ltd. | Pixel structure including a gate having an opening and an extension line between the data line and the source |
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