JPS61128531A - Manufacture of multilayer wiring substrate - Google Patents
Manufacture of multilayer wiring substrateInfo
- Publication number
- JPS61128531A JPS61128531A JP24985284A JP24985284A JPS61128531A JP S61128531 A JPS61128531 A JP S61128531A JP 24985284 A JP24985284 A JP 24985284A JP 24985284 A JP24985284 A JP 24985284A JP S61128531 A JPS61128531 A JP S61128531A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- polyimide film
- pattern
- film
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920001721 polyimide Polymers 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000203 mixture Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 abstract description 4
- 229920005575 poly(amic acid) Polymers 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 16
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 239000000243 solution Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 2
- 239000004327 boric acid Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- ing And Chemical Polishing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔殖東上の利用分野」
本発明は、多層配線基板の製造方法に係り、％に１ポリ
イミド膜のパターニング方法に関するＯ
〔従来の技術」
ポリイミド膜は、コーティーングが容易であること、優
れた轡械的保撞機能を具えていること等から、絶縁層と
し、て、あるいは電子デバイスのパッシベーシ−ン膜と
し【、広範囲にゎたる使用が期待されている。[Detailed Description of the Invention] [Field of Application of Shokutojo] The present invention relates to a method for manufacturing a multilayer wiring board, and relates to a method for patterning a 1% polyimide film. [Prior Art] A polyimide film is easy to coat. It is expected to be widely used as an insulating layer or as a passive basis film in electronic devices because of its excellent mechanical properties.
なかでも、このポリイミド膜の層間絶縁膜としての用途
は、ポリイミド膜の前駆体であるボリアツク酸は粘真な
液体であるため凹凸部に流れ込んで、次工程であるメタ
ル配線のための比較的平担な表面を形成することができ
るため、超大規模集積回路（ＶＬＩ３ｍ）中においては
、極めて１要な役割を果すものである。In particular, this polyimide film is used as an interlayer insulating film because boric acid, which is a precursor of the polyimide film, is a viscous liquid, so it flows into uneven areas and forms a relatively flat surface for the next process, metal wiring. Since it can form a flexible surface, it plays an extremely important role in very large scale integrated circuits (VLI3m).
眉間絶縁膜として使用する場合、基板表面生体ｉポリイ
ミド膜を塗布した後、更にレジストを塗布し、露光、現
像、エツチングによるポリイミド膜のパターン形成工程
へと吐くわけであるが、ポリイミド膜のパターン形成方
法とじては、■ポリイミド膜が完全に硬化した後に、ヒ
ドラジ／糸エッチャントを用いてエツチングする方法、
■ドライエツチング法、■レジストノ現像工程で同時に
エツチングする方法があげられろ。When used as an insulating film between the eyebrows, after applying a bio-i polyimide film to the substrate surface, a resist is further applied, and the pattern is formed by exposing, developing, and etching the polyimide film. Methods include: 1. After the polyimide film is completely cured, it is etched using a hydrazide/thread etchant;
■Dry etching method, ■Method of etching at the same time as the resist development process.
しかしながら、ヒドラジン系のエッチャントは、人体に
対して有害であり、使用に問題があった。また、ドライ
エツチング法は専用装置が必要であり、′ＩＢ層型イメ
ージセンサ等の如く大面積基板を用いる場合にはスルー
ブツト（処理能力）が低く、更には、レジストとの選択
比が°小さいためレジスト厚を厚くしなければならない
等の不都合があった。一方しシストの現像工程で同時忙
エツチングする方法は、ポリイミドをＢステージと指称
されている（ボリアツク酸塗布後約１４０Ｃで３０分間
加熱した〕状態ではポリイミドはレジストの現像液やア
ルカリ浴液に町浴であるため、このＢステージのポリア
ミド上にレジストを塗布し、露光した後、現像すると、
レジストパターングと共に、レジストの現像ｍ解した部
位の下部のポリイミドも同時にエツチングされることを
利用したものであるが、この場合、ポリイミドのエツチ
ングが進められていく際、レジストの現像も更に進み、
寸法精度が悪く、再現性が悪いという不都合があった０
本発明は、前記実情に鑑みてなされたもので、簡単な方
法で精度良く、ポリイミドのノ（ターン形成を行なうこ
とを目的とする。However, hydrazine-based etchants are harmful to the human body and have problems in use. In addition, the dry etching method requires specialized equipment, and when using a large-area substrate such as an IB layer image sensor, the throughput (processing capacity) is low, and furthermore, the selectivity with the resist is small. There were inconveniences such as the need to increase the resist thickness. On the other hand, the method of simultaneous etching in the cyst development process is called B stage (heating at about 140C for 30 minutes after application of boric acid), in which polyimide is not exposed to resist developer or alkaline bath solution. Since it is a bath, a resist is applied on this B-stage polyamide, exposed, and then developed.
This method takes advantage of the fact that, along with resist patterning, the polyimide underneath the developed area of the resist is also etched at the same time.In this case, as the etching of the polyimide progresses, the development of the resist also progresses.
The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to form polyimide turns in a simple manner and with high precision.
〔問題点を解決するための手段」
そこで、本発明では、ポリイミド膜を層間絶縁膜として
用いた多層配線基板の製造方法において、ポリイミド膜
上にレジストを塗布し露光した後、該レジストの）くタ
ーンの現像およびポリイミド膜のエツチングを行ないポ
リイミド膜のパターンを形成するにあたり、該レジスト
のパターンの現像工程とポリイミド膜のエツチング工程
が同一の現像液を用いて行なわれ、現像液の組成比が２
段階となるようにし、後段ではレジストとポリイミドの
エッチレートに選択比をもだせるようにしている。[Means for Solving the Problems] Therefore, in the present invention, in a method for manufacturing a multilayer wiring board using a polyimide film as an interlayer insulating film, after coating a resist on a polyimide film and exposing it to light, When developing the resist pattern and etching the polyimide film to form a polyimide film pattern, the resist pattern development step and the polyimide film etching step are performed using the same developer, and the composition ratio of the developer is 2.
In the latter stage, the etching rate of the resist and polyimide can be selectively selected.
すなわち、本発明はレジストの現像液を水で希釈する等
の方法によって組成比を変えることにより、レジストの
現像速度とポリイミドのエツチング速度に選択比をもた
せることができることに層目してなされたもので、工程
を前段と後段の２段階に分け、前段ではレジストの現偉
液ヲ用いてレジストの現像が行なわれ、下用部のレジス
トが除去されて下地のポリイミド膜が露呈した時点で、
例えば該現像液を水で希釈し、後段ではこの希釈液に代
えて、レジストの現像およびポリイミド膜のエツチング
が続行されるようにしている。That is, the present invention was made based on the fact that by changing the composition ratio by diluting the resist developer with water, etc., it is possible to provide a selectivity ratio between the resist development rate and the polyimide etching rate. The process is divided into two stages, the first stage and the second stage. In the first stage, the resist is developed using a resist developing solution. When the lower part of the resist is removed and the underlying polyimide film is exposed,
For example, the developer is diluted with water, and the diluted solution is used in the subsequent stage to continue developing the resist and etching the polyimide film.
これにより、後段ではレジストの現像速度に比ベポリイ
ミド膜のエツチング速度が速いため、レジストのパター
ンが過度にエツチングされて寸法変化を生じることなく
、ポリイミド膜Ｖ＞エツチングがなされるため、寸法精
度の良好なパターン形成が可能となる。As a result, since the etching speed of the polyimide film is faster than the developing speed of the resist in the subsequent stage, the resist pattern is not excessively etched and dimensional changes occur, and the polyimide film V is etched, resulting in good dimensional accuracy. This makes it possible to form a pattern.
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
まず、第１図（＝＝）に示す如（、セラミック基板１上
にボリアツク酸を塗布し、１４０Ｃで３０分ベーキング
することによりＢステージと指称されている半イミド状
態のポリイミド膜２（膜厚約２μｍ）を形成する。First, as shown in FIG. 1 (==), a polyimide film 2 in a semi-imide state (film thickness approximately 2 μm).
次いで、第１図（１））に示す如（、吏にこの上層に東
京も化製のポジ型フォトレジスト（３） ＯＦ Ｆ Ｒ
８００を約２μ塗布し、ベーキングした後、所定のフォ
トマスクを用いて露光しバターｙ像ｌを形成するり
この後、該ポジ型フォトレジスト３の現像液であ７［［
東名化製のＤｉｖ−ａをＤｍ７−３：水＝１：１となる
ように希釈した第１の溶液中に、該基板１を約１分間浸
漬し、第１図（Ｃ）に示す９口くレジストパターンを形
成する◎
続いて、レジストパターンの形成された該セラミック基
板を、・ＤＥｌｔＶ−３：水ミ１：３．５となるよ５に
更に希釈した第２のｍ液中に移し、第１図（ｄ）に示す
如（、ポリイミド膜２のエツチングを行なう。このとき
、レジストの現像もわずか（１，５μｍ以内）に退むが
、この現像速度は、ポリイミド膜のエツチング速度に比
べてはるかに小さい。Next, as shown in Fig. 1 (1)), a positive photoresist (3) manufactured by Tokyo Moka Co., Ltd. was applied to this upper layer.
After applying about 2 μm of 800 and baking, it was exposed using a prescribed photomask to form a buttery image L.
The substrate 1 was immersed for about 1 minute in a first solution in which Div-a (manufactured by Tomei Chemical Co., Ltd.) was diluted in a ratio of Dm7-3:water = 1:1. ◎ Next, the ceramic substrate on which the resist pattern has been formed is transferred to a second m solution further diluted to a ratio of DEltV-3:water 1:3.5. As shown in FIG. 1(d), the polyimide film 2 is etched. At this time, the development of the resist also recedes slightly (within 1.5 μm), but this development speed is compared to the etching speed of the polyimide film. much smaller.
このようにして形成されたポリイミド膜のパターンは、
寸法精度が良好であり、従来は１５μα 以下のパター
ンの形成は不可能であったのく対し約７μ のハターン
が精度良く形成される＠
また、現像液の組成比（希釈度）を変化させ、レジスト
（露光部）の現像速度とポリイミド膜のエツチング速度
を測定した結果を第２図に示す。図中、たて軸は現像速
度およびエツチング速度、横軸は現像液ＤＩｌ！σ−３
に対して加える水の割合を示す。レジストとしては０Ｆ
ＰＲＪ３ＱＱを２μ塗布したものを用い、夫々３（３）
５゜９゜露光したものを用いる。油取αは３ｗｍ１光し
た場合の現像速度曲線を示し、曲線すおよびＣも夫々５
ｓｅｃ４９ｓｅｃｍ光した場合の現像速度曲線を示す０
また、曲ａｐ工はポリイミド膜Ｐ Ｘ −２５５０を膜
厚２μとなるように塗布し、１４０ｔｌｌ’Ｔ−３゜分
加熱したもの）のエツチング速度曲線を示すＯこれらの
比較からも明らかなように、ＤＫＵ−３水−１：１とな
るように希釈された現像液ではレジストの現像速度が数
倍から１Ｏｖｒ程度大きいことがわかる。また露光量（
禦〕は、現像時間（ここでは１分間〕に対し、レジスト
寸法がマスク寸法と一致するような条件を選択するよう
にすればよい。The pattern of the polyimide film formed in this way is
The dimensional accuracy is good, and patterns with a diameter of approximately 7μ can be formed with good precision, whereas it was previously impossible to form patterns with a diameter of less than 15μα. FIG. 2 shows the results of measuring the development rate of the resist (exposed area) and the etching rate of the polyimide film. In the figure, the vertical axis is the development speed and etching speed, and the horizontal axis is the developer DIl! σ−3
Shows the ratio of water added to 0F as a resist
Using 2μ of PRJ3QQ, 3 (3)
Use those exposed at 5° and 9°. The oil removal α shows the development speed curve when the light is 3wm1, and the curves and C are also 5
0 showing the development speed curve when light is emitted at 49 seconds
In addition, the curve shows the etching rate curve of a polyimide film P It can be seen that the resist development speed is several times higher by about 1 Ovr when the developer is diluted with DKU-3 water to 1:1. Also, the exposure amount (
For the development time (here, 1 minute), conditions may be selected such that the resist dimensions match the mask dimensions.
更に、現像液の組成比（希釈度）を変化させ、レジスト
（′Ｉ４光部）の現像速度とポリイミド膜のエツチング
速度を測定した結果を第３図に示す。図中、たて軸は、
ポリイミドについてはエツチング速ｖ（Ａｌｉｎｓｅ）
および２μの膜厚のポリイミド膜のエツチングに要する
時間（分／２μ）、レジストについては寸法変化速度〔
ム／禦〕、４分後の寸法変化量（μ／４分）を示し、横
軸は、 ＤＫＵ−３を１としたとき加える水の割合を示
す口なおポリイミドおよびレジストは前記の例で使用し
た試料と同様にして形成したものを用いる。また、同様
に、曲線α、ｂ、ａは露光時間を夫々３ｓｅｅ ｅ ５
ｓｌＩｅ ｅ ９ｓｅｅとしたもの、曲ＮＰ工はポリイ
ミドについての測定結果を示すものである。この図から
明らかなように、現像液に対して加える水の割合が２．
５を越えると、し／ストの現像速度は大１ｍＫ低下し、
寸法変化速度も小さくなる一方、ポリイミドのエツチン
グ速度は、現像液（エツチング液）の希釈度には強くは
依存しない。従って、この範囲の現像液によればレジス
トの寸法変化を抑制しつつ、ポリイミドをエツチングし
、寸法精度の良好なポリイミドパターンを得ることが可
能となる０なお、レジストおよび現像液については、必
ずしも、実施例で用いた０ＦＰＲ−８ＱＱおよびＤＩＴ
Ｊ−３に限定されることなく、適宜選択可能であり、夫
々レジストに応じた現像液を選択し、現像液の濃度を２
段階に分け、主としてレジスト現像のための前段の工程
に比べ、主としてポリイミドのエツチングのための後段
の工程では、該現像液の濃度を適亘低くシ、レジストの
現像速度とポリイミドのエツチング速度に選択比をもた
せるようにすればよい。Furthermore, the composition ratio (dilution) of the developer was varied and the development rate of the resist ('I4 light area) and the etching rate of the polyimide film were measured, and the results are shown in FIG. In the figure, the vertical axis is
For polyimide, the etching speed v (Alinse)
and the time required for etching a polyimide film with a film thickness of 2μ (min/2μ), and the dimensional change rate for resist [
The dimensional change after 4 minutes (μ/4 min) is shown, and the horizontal axis is the ratio of water added when DKU-3 is 1. The polyimide and resist used in the above example are A sample formed in the same manner as the sample prepared above is used. Similarly, curves α, b, and a each have an exposure time of 3see e 5
slIe 9see and the curved NP work show the measurement results for polyimide. As is clear from this figure, the ratio of water added to the developer is 2.
When the value exceeds 5, the development speed of silica/st decreases by 1 mK,
While the rate of dimensional change also decreases, the etching rate of polyimide does not depend strongly on the degree of dilution of the developer (etching solution). Therefore, using a developer in this range, it is possible to etch polyimide while suppressing dimensional changes in the resist and obtain a polyimide pattern with good dimensional accuracy. 0FPR-8QQ and DIT used in the example
It is not limited to J-3, and can be selected as appropriate, by selecting a developer according to each resist, and setting the concentration of the developer to 2.
In the latter step, which is mainly for polyimide etching, the concentration of the developer is appropriately lowered and the resist development speed and polyimide etching speed are selected. All you have to do is make it proportional.
また、本発明では、ポリイミド膜は、元全罠イミド化さ
せることな（、Ｂステージと呼ばれている半イミド化段
階でパターニングし、その後、完全にイミド化させるよ
うにする。Further, in the present invention, the polyimide film is patterned at a semi-imidization stage called the B stage, and then completely imidized, without completely trap-imidizing the polyimide film.
更に、この工程は、自動現像装置を用いた場合には使用
するｍ液を途中で切り換えるのみでよく同一の現像装置
で、より作業性良く行なわれ得る。Furthermore, when an automatic developing device is used, this process can be carried out with better workability by simply changing the m liquid used midway through the process and using the same developing device.
以上、説明してきたように、本発明によｎば、ポリイミ
ド膜のパターン形成に除し、レジストパターンの現像工
程とポリイミド膜のエツチング工程とを、同一の現像液
を用い、濃度を２段階に分け、後段では前段よりも濃度
を低くするようにしているため、波設では、レジストの
寸法変化を抑制しつつポリイミド、ｎのエッチングが行
なわれ、寸法積置の良好なパターンが再現性良く形成さ
れ製造工数も低減される。As explained above, according to the present invention, in addition to forming a pattern on a polyimide film, the developing process for a resist pattern and the etching process for a polyimide film are performed using the same developer and in two stages of concentration. Since the concentration in the latter stage is lower than that in the previous stage, etching of polyimide and n is performed while suppressing dimensional changes in the resist, and a pattern with good dimensional stacking is formed with good reproducibility. This also reduces manufacturing man-hours.
第１内（α）乃至（ｔｉ′）は、本発明実施例のポリイ
ミドパターンの形成工程を示す図、第２図および第３図
は現像液の組成比（希釈度）と、レジストおよびポリイ
ミドの現像およびエツチング速度との関係を示し、第３
因は第２図の場合よりも更に現像液を希釈した場合を示
すものである・ｌ・・・セラミック基板、２−ポリイミ
ド膜、３・・・ポジ型フォトレジスト、４−フォトマス
ク、Ｙ・−パターン像。
第１図に）
第１図（ｂ）
第１図（Ｃ）
第１図（ｄ）
第２図
エト１水のｖｌ’２ｆｆ
加見る水の割１θFigures (α) to (ti') in Figure 1 are diagrams showing the process of forming a polyimide pattern in an example of the present invention. The relationship between development and etching speed is shown in the third section.
The reason is that the developer is diluted further than in the case of Fig. 2. L...Ceramic substrate, 2-Polyimide film, 3...Positive photoresist, 4-Photomask, Y... - Pattern image. In Figure 1) Figure 1 (b) Figure 1 (C) Figure 1 (d) Figure 2
Claims (1)
の製造方法において、基板表面に形成されたポリイミド
膜上にレジストを塗布し、露光した後、該レジストのパ
ターン現像工程、ポリイミド膜のエツチング工程を経て
ポリイミド膜のパターンを形成するに際し、該レジスト
のパターンの現像工程とポリイミド膜のエツチング工程
が、同一の現像液を用いた２段階の工程で行なわれ、後
段の工程では前段の工程で用いた現像液と組成比の異な
るものを用い、レジストの現像速度と、ポリイミド膜の
エッチング速度とに選択比をもたせるようにしたことを
特徴とする多層配線基板の製造方法。In a method for manufacturing a multilayer wiring board using a polyimide film as an interlayer insulating film, a resist is applied on a polyimide film formed on the surface of the substrate, exposed to light, and then subjected to a pattern development process for the resist and an etching process for the polyimide film. When forming a polyimide film pattern, the development process of the resist pattern and the etching process of the polyimide film are performed in two steps using the same developer, and the latter process uses the same developer as the one used in the previous process. 1. A method for manufacturing a multilayer wiring board, characterized in that a solution having a different composition ratio is used to provide a selectivity between a resist development rate and a polyimide film etching rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24985284A JPH0620064B2 (en) | 1984-11-27 | 1984-11-27 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24985284A JPH0620064B2 (en) | 1984-11-27 | 1984-11-27 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61128531A true JPS61128531A (en) | 1986-06-16 |
| JPH0620064B2 JPH0620064B2 (en) | 1994-03-16 |
Family
ID=17199143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24985284A Expired - Lifetime JPH0620064B2 (en) | 1984-11-27 | 1984-11-27 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620064B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008180425A (en) * | 2007-01-23 | 2008-08-07 | Chugoku Electric Power Co Inc:The | Ash transport pipe clogging preventing device for combustion ash or the like |
-
1984
- 1984-11-27 JP JP24985284A patent/JPH0620064B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008180425A (en) * | 2007-01-23 | 2008-08-07 | Chugoku Electric Power Co Inc:The | Ash transport pipe clogging preventing device for combustion ash or the like |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0620064B2 (en) | 1994-03-16 |
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