JPS59147430A - Formation of fine pattern - Google Patents
Formation of fine patternInfo
- Publication number
- JPS59147430A JPS59147430A JP1958183A JP1958183A JPS59147430A JP S59147430 A JPS59147430 A JP S59147430A JP 1958183 A JP1958183 A JP 1958183A JP 1958183 A JP1958183 A JP 1958183A JP S59147430 A JPS59147430 A JP S59147430A
- Authority
- JP
- Japan
- Prior art keywords
- electroless plating
- layer
- substrate
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000007772 electroless plating Methods 0.000 claims abstract description 24
- 239000003054 catalyst Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 229910021627 Tin(IV) chloride Inorganic materials 0.000 abstract description 3
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 abstract description 3
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 abstract description 3
- 239000004593 Epoxy Substances 0.000 abstract description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000919 ceramic Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 230000002349 favourable effect Effects 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000256011 Sphingidae Species 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は、無電解めっきにょシ微細なノやターンを形
成する微細回路の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for forming a fine circuit by forming fine grooves and turns using electroless plating.
（従来技術）
従来の微細回路の形成方法を第１図を参照して説明する
。(Prior Art) A conventional method for forming a fine circuit will be explained with reference to FIG.
第１図（ａ）において、１は基板であシ、まず、この基
板１上に触媒層２を形成する。この触媒層２は、たとえ
ば、塩化第２錫と塩化パラジウムの混合層を溶液処理で
付与するか、あるいは、パラジウムを蒸着によシ付与す
ることによシ形成される。In FIG. 1(a), 1 is a substrate, and first, a catalyst layer 2 is formed on this substrate 1. This catalyst layer 2 is formed, for example, by applying a mixed layer of stannic chloride and palladium chloride by solution treatment, or by applying palladium by vapor deposition.
しかる後、基板１を無電解めりき゛液中に浸漬すること
によシ、前記触媒層２上に無電解めっき被膜３を形成す
る。Thereafter, an electroless plating film 3 is formed on the catalyst layer 2 by immersing the substrate 1 in an electroless plating solution.
次に、無電解めっき被膜３上に７オトレソストを塗布し
て、それをフォトリン工程でパターン化することによシ
、第１図（ｂ）に示すように、フォトレジストパターン
４を無電解めっき被膜３上に形成する。Next, by applying 7 Otresost on the electroless plating film 3 and patterning it using a photoresist process, the photoresist pattern 4 is formed by electroless plating as shown in FIG. 1(b). Formed on the coating 3.
しかる後、フォトレジストパターン４をマスクとして無
電解めっき被膜３をエツチングすることによシ、残存無
電解めっき被膜３からなる微細な回路を第１図（ｃ）に
示すように形成する。なお、このエツチング後、前記フ
ォトレジストパターン４は除去される。第１図（Ｃ）は
フォトレジストパターン４を除去した後の状態を示して
いる。Thereafter, by etching the electroless plated film 3 using the photoresist pattern 4 as a mask, a fine circuit made of the remaining electroless plated film 3 is formed as shown in FIG. 1(c). Note that after this etching, the photoresist pattern 4 is removed. FIG. 1(C) shows the state after the photoresist pattern 4 has been removed.
以上の説明から明らかなように、従来の方法では、無電
解めっき被膜３をエツチングすることによシ微細な回路
を形成している。しかるに、そのエツチング時、サイド
エツチングが生じる。したがって、微細な回路を精度良
く形成できない欠点があった。また、ニッケル合金のよ
うな被膜で回路を形成したい時にも、被膜のエツチング
が困難なため、やはシ精度が悪い。As is clear from the above description, in the conventional method, fine circuits are formed by etching the electroless plating film 3. However, during etching, side etching occurs. Therefore, there was a drawback that fine circuits could not be formed with high precision. Furthermore, even when it is desired to form a circuit using a film such as a nickel alloy, etching the film is difficult, resulting in poor accuracy.
（発明の目的）
この発明は上記の点に鑑みなされたもので、無電解めっ
き被膜からなる微細な回路を精度よく形成できる微細回
路の形成方法を提供することを目的とする。(Objective of the Invention) The present invention has been made in view of the above points, and an object of the present invention is to provide a method for forming a fine circuit that can form a fine circuit made of an electroless plating film with high precision.
（実施例） 以下この発明の一実施例を第２図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
第２図（ＪＩＬ）において、１１はポリイミドフィルム
セラミックまたはガラスエポキシなどからなる基板であ
り、まず、この基板１１上に触媒層１２を形成する。こ
の触媒層１２は、たとえば、塩化第２錫と塩化パラジウ
ムの混合層を溶液処理で付与するか、あるいは、パラジ
ウムを蒸着によシ付与することによシ形成される。しか
る後、その触媒層１２上に７オトレソストを塗布して、
それをフォトリソ工程でパターン化することにより、フ
ォトレソストパターン１３を前記角虫媒層１２上に形成
する。In FIG. 2 (JIL), 11 is a substrate made of polyimide film ceramic or glass epoxy, and first, a catalyst layer 12 is formed on this substrate 11. This catalyst layer 12 is formed, for example, by applying a mixed layer of stannic chloride and palladium chloride by solution treatment, or by applying palladium by vapor deposition. After that, 7Otresost is applied on the catalyst layer 12,
A photoresist pattern 13 is formed on the hornworm medium layer 12 by patterning it using a photolithography process.
そして、そのフォトシソストパター／１３ヲｆｆスクと
して王水などの溶液によシ第２図（ｂ）に示すように触
媒層１２をエツチングすることにより、必要な回路以外
の触媒層ｊ２を除去する。Then, by etching the catalyst layer 12 with a solution such as aqua regia as a photolithographic cutter/13 offset, as shown in FIG. 2(b), the catalyst layer j2 other than the necessary circuits is removed. do.
しかる後、フォトレソストパターン１３を除去した上で
、無電解めっき液に浸漬して無電解めっきを行う。する
と、第２図（Ｃ）に示すように残存触媒層１２上にのみ
無電解めっき被膜１４が形成され、微細な回路が形成さ
れる。なお、無電解めっき被膜１４としては具体的には
無電解ニッケル被膜または無電解銅めっき被膜を形成す
る、（発明の効果）
以上の一実施例から明らかなように、この発明の方法に
おいては、必要な回路以外の触媒層を除去してから、残
存触媒層上に無電解めっきによシ無電解めっき被膜を形
成し、微細な回路を形成する。したがって、この発明の
方法によれは一無電循１めつき・被膜のエツチング工程
がなく、当然サイドエツチングがないので、徽細な回路
を精度良く形成できる。また、エツチング工程がないの
で、エツチングが困難なニッケル合金のような被膜で回
１１＜’；を形成する粋にも高精度を維持できる。さら
に、無電解めっきは、触媒層以外のところには付かない
ので、無電解めっき液の少しの変化に影響をれることな
く美顔な、めっき被膜の微細な回路を形成１２）ことが
できる。Thereafter, the photoresist pattern 13 is removed, and then electroless plating is performed by immersing it in an electroless plating solution. Then, as shown in FIG. 2(C), the electroless plating film 14 is formed only on the remaining catalyst layer 12, and a fine circuit is formed. In addition, as the electroless plating film 14, specifically, an electroless nickel film or an electroless copper plating film is formed. (Effects of the Invention) As is clear from the above embodiment, in the method of the present invention, After removing the catalyst layer other than the necessary circuits, an electroless plating film is formed on the remaining catalyst layer by electroless plating to form a fine circuit. Therefore, the method of the present invention does not require any electroless plating or film etching steps, and of course there is no side etching, so that fine circuits can be formed with high precision. Furthermore, since there is no etching step, high precision can be maintained even when the grooves 11<'; are formed using a film such as a nickel alloy that is difficult to etch. Furthermore, since electroless plating does not adhere to areas other than the catalyst layer, it is possible to form fine circuits in the plated film with a beautiful face without being affected by even the slightest change in the electroless plating solution12).
第１図は従来の微細回′路の形成方法を訝明する７Ｆ−
めの断面図、第２図はこの発明の微細回路の形成方法の
一実施例を説明するための断面図である。
１１・・・基板、１２・・・触媒層、１３・・フォトレ
ジ゛ストパタ〜ン、１４・・・無電解めっき被膜。
特許出願人 沖電気ユ、業株式会社
第１図
第２図FIG.
FIG. 2 is a cross-sectional view for explaining one embodiment of the method for forming a fine circuit according to the present invention. DESCRIPTION OF SYMBOLS 11... Substrate, 12... Catalyst layer, 13... Photoresist pattern, 14... Electroless plating film. Patent applicant: Oki Electric Co., Ltd. Figure 1 Figure 2
Claims (1)
、その触媒層を必要な筒所以外除去する工程と、残存触
媒層上に無電解めっきＫより無電解めっき被膜を形成す
る工程とを具備してなる微細回路の形成方法。A step of forming a layer to serve as a catalyst for electroless plating on a substrate, a step of removing the catalyst layer except for necessary areas, and a step of forming an electroless plating film by electroless plating K on the remaining catalyst layer. A method for forming a microcircuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1958183A JPS59147430A (en) | 1983-02-10 | 1983-02-10 | Formation of fine pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1958183A JPS59147430A (en) | 1983-02-10 | 1983-02-10 | Formation of fine pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59147430A true JPS59147430A (en) | 1984-08-23 |
Family
ID=12003227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1958183A Pending JPS59147430A (en) | 1983-02-10 | 1983-02-10 | Formation of fine pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59147430A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07509347A (en) * | 1992-07-09 | 1995-10-12 | レイケム・コーポレイション | electrical equipment |
| KR100867419B1 (en) | 2007-07-12 | 2008-11-06 | 한국기계연구원 | Manufacturing method of patterned flexible copper clad laminate |
| CN103929903A (en) * | 2013-01-15 | 2014-07-16 | 日本特殊陶业株式会社 | Method for manufacturing wiring substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4990640A (en) * | 1972-12-20 | 1974-08-29 | ||
| JPS5884964A (en) * | 1981-11-16 | 1983-05-21 | Seiko Epson Corp | Production of pattern plating on insulator |
-
1983
- 1983-02-10 JP JP1958183A patent/JPS59147430A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4990640A (en) * | 1972-12-20 | 1974-08-29 | ||
| JPS5884964A (en) * | 1981-11-16 | 1983-05-21 | Seiko Epson Corp | Production of pattern plating on insulator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07509347A (en) * | 1992-07-09 | 1995-10-12 | レイケム・コーポレイション | electrical equipment |
| KR100867419B1 (en) | 2007-07-12 | 2008-11-06 | 한국기계연구원 | Manufacturing method of patterned flexible copper clad laminate |
| CN103929903A (en) * | 2013-01-15 | 2014-07-16 | 日本特殊陶业株式会社 | Method for manufacturing wiring substrate |
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