JPS6014453A - Forming method of metallic layer pattern - Google Patents

Forming method of metallic layer pattern

Info

Publication number
JPS6014453A
JPS6014453A JP12100183A JP12100183A JPS6014453A JP S6014453 A JPS6014453 A JP S6014453A JP 12100183 A JP12100183 A JP 12100183A JP 12100183 A JP12100183 A JP 12100183A JP S6014453 A JPS6014453 A JP S6014453A
Authority
JP
Japan
Prior art keywords
layer
resist
metal layer
platinum
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12100183A
Other languages
Japanese (ja)
Inventor
Kazuto Ogasawara
和人 小笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12100183A priority Critical patent/JPS6014453A/en
Publication of JPS6014453A publication Critical patent/JPS6014453A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form a fine wiring pattern thickly by applying a first metallic layer on a substrate, selectively plating the first metallic layer with a second metallic layer, evaporating a third metallic layer on the second metallic layer and etching the first metallic layer while using the third metallic layer as a mask. CONSTITUTION:A chromium layer 2, a first platinum layer 3 and a first gold layer 4 are evaporated on an insulating substrate 1, and a resist film 5 is formed, and patterned. A second gold layer 6 is applied on the surface of the exposed gold layer 4 through electroplating, and a second platinum layer 7 is formed through an evaporation on the whole surface. The resist 5 is dissolved and removed, the first gold layer 4 is etched selectively while using the second platinum layer 7 as a mask, and the second platinum layer 7, the first platinum layer 3 and the chromium layer 2 are removed through ion milling, thus forming a precise pattern of a metallic wiring in approximately 6-8mum thickness.

Description

【発明の詳細な説明】 技術分野 本発明は金属パターンの形成方法に係シ、特にマイクロ
波回路などの配線に用いる厚い金属配線の形成方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method of forming a metal pattern, and more particularly to a method of forming a thick metal wiring used for wiring such as a microwave circuit.

技術の背景 マイクロ波回路では大電力大電流が流れるので配線の抵
抗が太きいと電力の損失も大きく、配線の焼き切れなど
の問題がある。配線の抵抗は配線の断面積に比例するが
、装置が高密度化する最近の傾向の下では配線の幅を小
さくせざるを得す。
Background of the Technology In microwave circuits, large amounts of power and current flow, so if the resistance of the wiring is large, the loss of power will be large and there will be problems such as burnout of the wiring. The resistance of wiring is proportional to the cross-sectional area of the wiring, but with the recent trend towards higher density devices, the width of the wiring has to be reduced.

従って、厚い配線を形成する必要がある。又、スキッデ
ブスの点から高周波が配線表面を伝搬する場合実際には
ある程度の厚みが必要であり、特に1〜10 GHzで
は特に厚くする必要がある。
Therefore, it is necessary to form thick wiring. Furthermore, from the point of view of Skidbus, a certain amount of thickness is actually required when high frequency waves propagate on the wiring surface, and it is particularly necessary to increase the thickness in the range of 1 to 10 GHz.

従来技術と問題点 従来、配線層を厚く形成するには、単純には。Conventional technology and problems Conventionally, forming a thick wiring layer was simply done.

厚く被着した金属層の上にレジスト全塗布し、バターニ
ングし、そのレジストに用いて金属層をエツチングする
方−悲がある。しかし、エツチングの際どうしても金属
層がサイドエッチされるので厚い金属層に微細なパター
ンを精密に作成することは困難である。又他の方法とし
て、全面に薄く金属層を蒸着後厚くレジスト全塗布し、
それをパターニングして露出した金属層上に選択的にメ
ッキを施し、レジストを除去し、露出した蒸着金属を選
択的に除去する手法がある。しかし、この方法でも、現
在Vジストラ約3μmJl:、!7厚く成膜できないの
で1選択メッキ法で良好に作成できる金属層の厚さも限
られている。というのは、レジストの厚さ金越えて堆積
されるメッキ層はもはやレジストのパターンによる横方
向の制約を受けないので接床が9に々シ、微細なパター
ンの作成全困難にする。又1選択メッキすべき基層に高
い段差(ステップ)がある場合、その上にレジストヲ塗
布してもステップ部分を完全に覆うことができずステッ
プ肩部の基層が露出するので、不所望な位置にメッキが
付着する等のステップカバレージの問題があるからであ
る。
There is a method of completely applying a resist on a thickly deposited metal layer, buttering it, and then using the resist to etch the metal layer. However, since the metal layer is inevitably side-etched during etching, it is difficult to precisely form fine patterns on a thick metal layer. Another method is to deposit a thin metal layer on the entire surface and then apply a thick resist to the entire surface.
There is a method of patterning the resist, selectively plating the exposed metal layer, removing the resist, and selectively removing the exposed evaporated metal. However, even with this method, the current Vzistra is about 3 μmJl:,! 7. Since it is not possible to form a thick film, the thickness of the metal layer that can be satisfactorily formed by the one-select plating method is also limited. This is because a plating layer deposited beyond the thickness of the resist is no longer constrained in the lateral direction by the pattern of the resist, so that the contact with the plate is as short as 9 times, making it extremely difficult to create fine patterns. In addition, if there is a high step in the base layer to be selectively plated, even if a resist is applied on top of it, it will not be able to completely cover the step part and the base layer at the shoulder of the step will be exposed, leaving it in an undesired position. This is because there are problems with step coverage such as adhesion of plating.

発明の目的 本発明は1以上の如き従来技術の現状に鑑み。Purpose of invention The present invention is in view of one or more of the current state of the art.

3μm以上の厚さを有する微細配線(金属層)パターン
を形成する方法を提供することを目的とする。
It is an object of the present invention to provide a method for forming a fine wiring (metal layer) pattern having a thickness of 3 μm or more.

発明の構成 そして、上記目的を達成するために1本発明は。Composition of the invention One aspect of the present invention is to achieve the above object.

基板上に第一の金属層全被着し、その上にレジストを選
択的に塗布し、そのレジストのパターンを利用して第二
の金属層全選択的に第一の金属層の露出表面上のみにか
つレジストの厚みよシも薄くメッキし、第二の金属層お
よびレジストの上全面に第三の金属層を蒸着し、レジス
トを溶解してその上にある第三の金属層と共に除去し、
そして第三の金属層の残存部分音マスクとして第一の金
属層全選択的にエツチングする工程を含む方法を提供す
る。
A first metal layer is fully deposited on the substrate, a resist is selectively applied thereon, and a second metal layer is selectively applied over the exposed surface of the first metal layer using the pattern of the resist. A third metal layer is deposited on the second metal layer and the entire surface of the resist, and the resist is dissolved and removed together with the third metal layer on top of the resist. ,
A method is then provided which includes selectively etching the entire first metal layer as a residual partial mask for the third metal layer.

以下1発明の実施(例を用いて説明する。Implementation of one invention will be described below using an example.

発明の実施例 第1図において1例えば、アルミナまたはサファイアな
どよりなる絶縁性基板1の全面にわたってクロム層2.
第1の白金層3.そして第1の金属層4の順に蒸着する
。クロム層2は絶縁基板との接着性を良くするため、白
金属3はクロムと金の間の不都合な反応を抑止するため
に用いる。各層の厚さは、順に、クロム層2が500〜
700X・白金層3が500〜tooo′A、金層4が
4〜6μmである。次いで、ネガ形レジスト例えばシラ
プレー社の商品AZ1350を回転数1.50Or、p
、m、でスピンコードし厚さ3μmのレジスト膜6を形
成し、パターニングする。レジストを除1去する部分即
ち配線を形成すべき部分の幅は1例えば、15μmであ
る。
Embodiment of the Invention In FIG. 1, a chromium layer 2 is formed over the entire surface of an insulating substrate 1 made of, for example, alumina or sapphire.
First platinum layer3. Then, the first metal layer 4 is deposited in this order. The chromium layer 2 is used to improve adhesion to the insulating substrate, and the white metal 3 is used to suppress undesirable reactions between chromium and gold. The thickness of each layer is as follows: chromium layer 2 has a thickness of 500~
700X, the platinum layer 3 has a thickness of 500 to too'A, and the gold layer 4 has a thickness of 4 to 6 μm. Next, a negative resist, for example, AZ1350 manufactured by Silaplay Co., Ltd., was applied at a rotation speed of 1.50 Orp, p.
, m, to form a resist film 6 having a thickness of 3 μm and patterning. The width of the portion where the resist is removed, that is, the portion where wiring is to be formed, is, for example, 15 μm.

第2図において、上記基板を電解メッキ浴で処理してレ
ジスト6の間に露出した白金層5の表面上に第2の金層
7全厚さ2μm程度選択的に被着スル。メッキ浴から取
り出し、洗浄後、レジスト5および第2の金層6の上か
ら全面に蒸着して第2の白金層7を厚さ500〜100
OXに形成する。
In FIG. 2, the substrate is treated with an electrolytic plating bath to selectively deposit a second gold layer 7 on the surface of the platinum layer 5 exposed between the resists 6 to a total thickness of about 2 μm. After removing from the plating bath and cleaning, a second platinum layer 7 is deposited on the entire surface from above the resist 5 and the second gold layer 6 to a thickness of 500 to 100 mm.
Form into OX.

第3図において、上記基板にアセトンを吹き付けてレジ
スト5を溶解除去すると、レジスト5の上に蒸着されて
いた第2の白金層7も一緒に除去される。
In FIG. 3, when the resist 5 is dissolved and removed by spraying acetone onto the substrate, the second platinum layer 7 deposited on the resist 5 is also removed together.

次に、第4図において、基板をヨード+ヨウ化カリウム
液に浸漬バブリングすると、第2の白金層7がマスクと
なって第1の金層4が選択的にエツチングされる。続い
て、第5図において、Arガスによるイオンミリングで
第2の白金層7およびヨウド+ヨウ化カリウム液の工多
チングで露出した第1の白金層3を除去し、それから更
に露出したクロム層2’iArによるイオンミリングに
よυ選択的に除去する。
Next, in FIG. 4, when the substrate is immersed in an iodine+potassium iodide solution and bubbled, the first gold layer 4 is selectively etched using the second platinum layer 7 as a mask. Subsequently, in FIG. 5, the second platinum layer 7 is removed by ion milling using Ar gas, and the exposed first platinum layer 3 is removed by milling with an iodine + potassium iodide solution, and then the exposed chromium layer is removed. υ selectively removed by ion milling with 2'iAr.

こうして、絶縁性基板1の上に厚さ約6〜8μmの金属
配線の精密な15μm巾のパターンが形成される。パタ
ーンの上端で11μm、下端部で13μm程度の幅であ
る。
In this way, a precise 15 μm wide pattern of metal wiring with a thickness of about 6 to 8 μm is formed on the insulating substrate 1. The width is approximately 11 μm at the upper end of the pattern and 13 μm at the lower end.

選択的に、上記のリフトオフ即ちレジスト5の除去後1
例えばニッケル、銀等を全面に即ち第2の金層6の側面
も含めて薄くメッキし、ミリングで第1の金層4および
第2の白金層70面上のメッキ層だけを除去してから、
第1の金層4のバブルエツチングを行なえば、第2の金
層6の側面にはメッキ層が残っているのでサイドエッチ
量が無視できる程度に少なくiる。
Optionally, after the above-mentioned lift-off or removal of the resist 5 1
For example, the entire surface of the second gold layer 6 is plated with a thin layer of nickel, silver, etc., including the side surfaces of the second gold layer 6, and only the plating layer on the first gold layer 4 and the second platinum layer 70 is removed by milling. ,
If bubble etching is performed on the first gold layer 4, the plating layer remains on the side surfaces of the second gold layer 6, so that the amount of side etching is reduced to a negligible extent.

更に1選択的に、第2の白金層7に換えてチタン、クロ
ム等を用いれば、金との選択比が大きいのでリアクティ
ブイオンエツチングを用いて、チタン、クロム等の層7
をマスクとする第1の金層4の選択的エツチングが可能
である。これによって、サイドエッチ量はさらに少なく
なシ、パターン精度が向上する。
Furthermore, if titanium, chromium, etc. are used instead of the second platinum layer 7, the selectivity with gold is high, so reactive ion etching is used to remove the layer 7 of titanium, chromium, etc.
Selective etching of the first gold layer 4 is possible using as a mask. This further reduces the amount of side etching and improves pattern accuracy.

発明の効果 以上の説明から明らかなように1本発明に依シ、膜厚が
3μmを越える金属層のパターンをパターン0幅やパタ
ーン間隔が狭くなっても精度良く形成することができる
Effects of the Invention As is clear from the above description, depending on the present invention, it is possible to form a pattern of a metal layer having a film thickness exceeding 3 μm with high accuracy even if the pattern width and the pattern interval are narrow.

【図面の簡単な説明】[Brief explanation of drawings]

第1〜5図は本発明の詳細な説明するための配線パター
ン形成の工程順の断面図である。 1・・・基板、2・・・クロム層、3・・・第1の白金
層。 4・・・第1の金層、5・・・レジスト、6・・・第2
の金層。 7・・・第2の白金層。 第1図 第2図 第3図 昏4図
1 to 5 are cross-sectional views showing the steps of forming a wiring pattern for explaining the present invention in detail. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Chromium layer, 3...1st platinum layer. 4... First gold layer, 5... Resist, 6... Second
gold layer. 7...Second platinum layer. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 基板上に第一の金属層を被着し、その上にレジストを選
択的に塗布し、そのレジストのパターンを利用して第二
の金属層を選択的に前記第一の金属層の露出表面上のみ
にかつ前記レジストの厚みよシも薄くメッキし、該第二
の金属層および前記レジストの上全面に第三の金属層を
蒸着し、前記レジタ)f溶解してその上にある前記第三
の金属層と共に除去し、そして前記第三の金属層の残存
部分をマスクとして前記第一の金属層を選択的にエツチ
ングする工程を含むことを特徴とする金属層パターンの
形成方法。
A first metal layer is deposited on a substrate, a resist is selectively applied thereon, and a pattern of the resist is used to selectively apply a second metal layer to the exposed surface of the first metal layer. A third metal layer is deposited on the second metal layer and the entire surface of the resist, and the resist is melted to remove the second metal layer on top of the resist. A method for forming a metal layer pattern, comprising the steps of removing the first metal layer together with the third metal layer, and selectively etching the first metal layer using the remaining portion of the third metal layer as a mask.
JP12100183A 1983-07-05 1983-07-05 Forming method of metallic layer pattern Pending JPS6014453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12100183A JPS6014453A (en) 1983-07-05 1983-07-05 Forming method of metallic layer pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12100183A JPS6014453A (en) 1983-07-05 1983-07-05 Forming method of metallic layer pattern

Publications (1)

Publication Number Publication Date
JPS6014453A true JPS6014453A (en) 1985-01-25

Family

ID=14800321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12100183A Pending JPS6014453A (en) 1983-07-05 1983-07-05 Forming method of metallic layer pattern

Country Status (1)

Country Link
JP (1) JPS6014453A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63161646A (en) * 1986-12-25 1988-07-05 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH0334324A (en) * 1989-06-29 1991-02-14 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63161646A (en) * 1986-12-25 1988-07-05 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH0334324A (en) * 1989-06-29 1991-02-14 Nec Corp Manufacture of semiconductor device

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