JPS61124157A - 半導体装置用キヤツプ・フレ−ム - Google Patents

半導体装置用キヤツプ・フレ−ム

Info

Publication number
JPS61124157A
JPS61124157A JP59245312A JP24531284A JPS61124157A JP S61124157 A JPS61124157 A JP S61124157A JP 59245312 A JP59245312 A JP 59245312A JP 24531284 A JP24531284 A JP 24531284A JP S61124157 A JPS61124157 A JP S61124157A
Authority
JP
Japan
Prior art keywords
cap
frame
caps
resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59245312A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0351300B2 (enrdf_load_stackoverflow
Inventor
Eiji Hagimoto
萩本 英二
Koji Nagao
長尾 工司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59245312A priority Critical patent/JPS61124157A/ja
Publication of JPS61124157A publication Critical patent/JPS61124157A/ja
Publication of JPH0351300B2 publication Critical patent/JPH0351300B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP59245312A 1984-11-20 1984-11-20 半導体装置用キヤツプ・フレ−ム Granted JPS61124157A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59245312A JPS61124157A (ja) 1984-11-20 1984-11-20 半導体装置用キヤツプ・フレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59245312A JPS61124157A (ja) 1984-11-20 1984-11-20 半導体装置用キヤツプ・フレ−ム

Publications (2)

Publication Number Publication Date
JPS61124157A true JPS61124157A (ja) 1986-06-11
JPH0351300B2 JPH0351300B2 (enrdf_load_stackoverflow) 1991-08-06

Family

ID=17131797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59245312A Granted JPS61124157A (ja) 1984-11-20 1984-11-20 半導体装置用キヤツプ・フレ−ム

Country Status (1)

Country Link
JP (1) JPS61124157A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63174340A (ja) * 1987-01-13 1988-07-18 Ibiden Co Ltd 半導体装置
JPH0529152U (ja) * 1992-08-07 1993-04-16 イビデン株式会社 電子部品装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63174340A (ja) * 1987-01-13 1988-07-18 Ibiden Co Ltd 半導体装置
JPH0529152U (ja) * 1992-08-07 1993-04-16 イビデン株式会社 電子部品装置

Also Published As

Publication number Publication date
JPH0351300B2 (enrdf_load_stackoverflow) 1991-08-06

Similar Documents

Publication Publication Date Title
US5322207A (en) Method and apparatus for wire bonding semiconductor dice to a leadframe
CN207781575U (zh) 经封装的电子装置
US8071426B2 (en) Method and apparatus for no lead semiconductor package
US5034350A (en) Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
US5652185A (en) Maximized substrate design for grid array based assemblies
US6462273B1 (en) Semiconductor card and method of fabrication
US6376277B2 (en) Semiconductor package
US6175149B1 (en) Mounting multiple semiconductor dies in a package
JPS629639A (ja) 半導体装置の製造方法
EP0923120A1 (en) Method for manufacturing semiconductor device
JP2002050645A (ja) 半導体装置の製造方法
KR20050066999A (ko) 반도체장치 및 그 제조방법
JPS61124157A (ja) 半導体装置用キヤツプ・フレ−ム
US6475878B1 (en) Method for singulation of integrated circuit devices
US10079162B1 (en) Method for making lead frames for integrated circuit packages
JPH08227964A (ja) リードフレーム、半導体集積回路装置、半導体集積回路装置製造方法及び半導体集積回路装置製造装置
JP3243951B2 (ja) 電子部品の製造方法
US8106489B1 (en) Integrated circuit package and packaging method
US20150206829A1 (en) Semiconductor package with interior leads
JPH0831998A (ja) 半導体装置およびその製造に用いるリードフレームならびにワイヤボンディング装置
JP2000349187A (ja) 半導体装置及び半導体装置の製造方法
JP2001144036A (ja) Icチップのパッケージ方法
JPH113963A (ja) 樹脂封止型半導体装置及びリードフレーム
JP2000077450A (ja) 半導体装置およびその製造方法
JPH0770640B2 (ja) Icチップの製造方法