JPS61123229A - Data transmission system - Google Patents

Abstract

PURPOSE:To relieve the load of a compuer at the reception side by transmitting a specific pattern detected at a slow sampling period before the data is transmitted to the reception side so as to change the sampling period of the computer of the reception side. CONSTITUTION:The reception side samples data in a speed being nearly 1/4 of the transmissin speed normally and when two consecutive '0s' are found out, it is regarded as NULL code detection and the sampling speed is brought into the data transmission speed. When a stop bit is found out, the sampling interval is increased to four times that of the transmission speed, and further, when a start bit is found out, the sampling interval is brought into two times that of the transmision speed. When it is confirmed that the data is '0', the data is sampled in the data sampling speed to receive the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a data transmission system that uses a software method to transmit data in an asynchronous manner.

Here, the structure of the asynchronous signal and the main parts of a general data transmitting/receiving circuit will be explained.

FIG. 2 is a block diagram of a signal in an asynchronous system, and FIG. 3 is a block diagram of a main part of a general data transmitting/receiving circuit.

In the figure, 1 is MPU, 2 is address decoder, 3 is ROM
, 4 is a RAM, 5 is an input/output device, 6 is a timer, 7 is an address bus, and 8 is a data bus.

As shown in Figure 2, the asynchronous signal line is normally held at 1 level, and when transmitting data, a 1-bit θ level starts before and after the 7 to 10 bits of data that make up one character. The receiving side uses the start bit to start start-stop synchronization, and the stop bit to stop the synchronization.

The following explanation assumes that the start bit and stop bit are each 1 bit, and the data is 8 bits.

Next To explain the basic operation of the data transmitting/receiving circuit shown in Figure 3, the MPUI first outputs the corresponding address to the address bus 7 in order to read an instruction stored in the ROM 3, and the address decoder 2 It decodes the address and outputs a chip select signal to ROM3.

When the ROM 3 receives the chip select signal, it outputs the instruction stored at the corresponding address to the data bus 8.

The MPUI inputs this command and executes the command.

Reading data from the RAM 4 and the input/output device 5 is performed in the same manner as above, and when attempting to output data thereto, the MPUI outputs the address and data to the address bus 7 and data bus 8, respectively. The decoder 2 has RAM4. A chip select signal is output to one of the input/output devices 5, and a write timing signal is output to the RAM 4. - The input/output device 5 reads data on the data bus 8 in synchronization with this write timing signal.

- For example, when you type in the data you want to send from a keyboard (not shown), it is written to RAM4 via data bus 8 and stored in ROM3, which is controlled by MPUI. This is read out according to the program to be sent, a start bit and a stop bit are added, and it is sent to the other party via the input/output device 5.

The signal received from the other party is sent manually to the input/output device 5, which finds the start bit and starts start/stop synchronization.
≠ - evening is received from the UI at the sampling period set in the timer 6 and written into the RAM 4.

The timing of sampling in this case is controlled by the MPU 1 by setting the timer 6 according to a program instruction and performing an interrupt.

Data is transmitted and received in this way, and in this case, it is desirable that the load on the computer on the receiving side be reduced so that it can perform other tasks.

[Conventional technology]

Figure 4 is a diagram showing the signals and sampling speeds of each part when receiving conventional data.When receiving conventional data, create a program to change the sampling rate as shown below and store it in ROM3 in Figure 3. Then, the timing of this sampling is set in the timer 6 under the control of the MPUI shown in FIG. 3, and an interrupt is generated and received.

To explain the operation in correspondence with ■ to ■ in Figure 4, ■As shown in ■ in Figure 4, normally the start bit is found at least four times the data transmission speed even if there is noise. When the start bit is found, the sampling interval is changed to twice the transmission speed and the process moves to (2).

(2) Sample the data and confirm that it is O level. If it is O level, set the sampling interval to the transmission speed and move to (2).

If it is not 0, it is determined that the previously found 0 was an erroneous signal due to noise, and the process returns to (2).

■Set the sampling interval to the transmission speed up to the stop bit,
Data is received, and after detecting a stop bit, the sampling period is set to four times the data transmission speed and returns to step (3).

(Problems to be Solved by the Invention) However, in the above method, sampling must be performed at four times the data transmission speed when normal data reception is not being performed, resulting in a large number of interruptions and The MPUI shown in the figure has the problem of increasing the software processing load and reducing the amount of other work being done.

[Means for solving problems]

The above problem is that on the transmitting side, before sending data, □ a 0-level signal that can perform sampling at a rate slower than the data sampling rate at least twice, and following this signal, sampling at least once at the data sampling rate. 1 level signal is sent out, and the receiving side normally performs sampling at a slower rate than the above data sampling rate, and when a θ level signal is detected twice in succession, the sampling rate 1
This problem is solved by the data transmission method of the present invention, in which sampling is performed at the data sampling rate until a level signal is detected, and thereafter, sampling is performed to find the start point and node.

[Effect]

According to the present invention, before sending data, there is an O level signal that allows sampling at a rate slower than the data sampling period at least twice, and a 1 level signal that allows sampling at least once at the data sampling rate following this signal. A signal is sent, and on the receiving side, after finding these 0 level and 1 level signals, sampling is performed at four times the transmission speed as before to find the start bit, so normal data is not received. At the time,
It is sufficient to perform sampling at a speed slower than the data sampling cycle, which reduces the number of interruptions, reduces the software processing load, and allows more work to be done.

〔Example〕

FIG. 1 is a diagram showing the signal and the sampling speed of each part when receiving data according to the embodiment of the present invention. In this case, before transmitting data, an asynchronous signal structure is
This is an example in which a ULL code (all O's) is transmitted.

In this case, the sending program inserts a NULL code before sending the data, and the third
This is executed by storing it in the ROM 3 shown in the figure.

On the receiving side, create a program for changing the sampling interval as shown below and store it in ROM3 in Figure 3.
This timing is set in the timer 6 under the control of the MPU 1 shown in FIG. 3 to cause an interrupt to be generated and received.

Hereinafter, the operations will be explained in correspondence with ① to ② in FIG.

■Normally, sampling is performed at a speed of about 1/4 of the data transmission speed, and when a second 0 is found in a row, NUL is detected.
For L code detection, set the sampling rate to the data transmission rate and proceed to step (3).

■Sampling is performed at the data transmission speed and repeats this until a stop bit is found.When the stop bit is found, the sampling interval is increased to four times the transmission speed,■
Move to.

■Sampling is performed with four times the data and repeating this process until the start bit is found. After finding the start bit, set the sampling interval to twice the transmission rate and move on to step (3).

■Confirm that the data is O (9), set the sampling to the data transmission speed, and proceed to ■. If the data is 1, ■
It is determined that the O found in is not the start bit, and ■
Return to

■Perform sampling at the data transmission speed and receive data. This is repeated until the stop bit is reached, and after the stop bit is detected, the process returns to ■.

Data is received in this way, so in normal cases when data is not being received, it is only necessary to sample at a slower rate than the data sampling rate (compared to the conventional MPUI software shown in Figure 3). The processing load will be reduced and you will be able to do other tasks.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the load on the combinator on the receiving side is reduced.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the signal and sampling speed of each part when receiving data according to the embodiment of the present invention, Fig. 2 is a diagram showing the configuration of the signal of the start-stop synchronization method, and Fig. 3 is a diagram showing the general data transmission and reception. A block diagram of the main parts of the circuit, FIG. 4 is a diagram showing signals and sampling speeds of each part when receiving data in a conventional example. In the figure, 1 is an MPU. 2 is an address decoder, 3 is a ROM. 4 is RAM. 5 is an input/output device, 6 is a timer, 7 is an address bus, and 8 is a data bus. Calculation 1 Figure 2! 4 Figure

Claims (1)

[Claims] When transmitting data using the start-stop synchronization method, on the transmitting side,
Before sending the data, a 0-level signal that allows sampling at a rate slower than the data sampling rate at least twice, and a 1-level signal that allows sampling at least once at the data sampling rate following this signal, On the receiving side, sampling is normally performed at a slower rate than the data sampling rate mentioned above, and when a 0-level signal is detected twice in a row, the sampling rate is changed to the rate at which a 1-level signal is detected. A data transmission method characterized in that sampling is performed at the data sampling rate until the start bit is reached, and thereafter sampling is performed to find the start bit.