JPS61123183A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the irregularities of the thickness of a resist layer, and to improve the degree of integration of a gate electrode by formig the resist layer having the same etching rate as a gate electrode material onto a gate electrode material layer directly or just after patterning and flattening the whole surface. CONSTITUTION:A field oxide film 22 is formed onto a P type Si substrate 21, a gate oxide film 24 is shaped into an element region 23, a polycrystalline silicon layer 25 and a resist layer 26 having the same etching rate as the layer 25 are formed onto the whole surface, and the whole surface is flattened. The layers 26, 25 are etched through reactive ion etching until the surface of the field oxide film 22 is exposed. A resist pattern 27 is shaped onto the layer 25, the layer 25 is removed selectively through etching while using the resist pattern 27 as a mask to form a gate electrode 28, the film 24 is removed while employing the gate electrode 28 as a mask, and an N type impurity is introduced to the substrate 21 while using the electrode 28 as a mask to form N<+> type source-drain regions 29, 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is characterized by a special feature of Kf-)! % to a method of manufacturing a semiconductor device with improved electrode formation.

[Technical background of the invention]

Conventionally, the S-type transistor has been proposed, for example, as shown in FIG.
c), manufactured as shown in FIGS. 5 and 6.

First, a field oxide film 2 is formed on the surface of a P-type semiconductor substrate 10, for example. Next, this field - oxide film 2
After forming an oxide film 4 on the element region 3 of the substrate surrounded by , a polycrystalline silicon layer 5 is formed on the entire surface (as shown in FIG. 4(a)).

Next, a resist layer 6 is formed on the polycrystalline silicon layer 5 (as shown in FIG. 4(b)). Thereafter, exposure and development are performed to form a renost/arm turn (not shown), and then the polycrystalline silicon layer 5 is selectively etched away using this pattern as a mask to form a P-tall made of polycrystalline silicon. Electrode 7 ft: Formed. Furthermore, the Rennost pattern is peeled off, and the gate oxide film 4 is removed using the r-upper electrode 7 as a mask.
selectively remove. Subsequently, using the r- upper electrode 7 as a mask, n-type impurities are introduced into the substrate 1, and N+! The source and drain regions 8.9 of j1 are formed to form a MO8O8 type transistor (as shown in FIGS. 4(C), 5, and 6). Here, FIG. 5 is a plan view of Cel in FIG. 4, and FIG. 6 is a sectional view taken along the line X--X in FIG.

[Problems with background technology]

However, according to the conventional MO8 type trannostar,
As the gate z-pole becomes finer with the increase in the degree of integration of semiconductor integrated circuits, the
1 needs to be long enough to extend over the flat portion of the field oxide film 2, which poses a problem in that the spacing between elements or the spacing between elements and wiring cannot be narrowed. This will be explained in detail below. That is, conventionally, r-)! Since the polycrystalline silicon layer 5 serving as the pole also extends over the field oxide film 2, it is formed with unevenness, and as a result, the silenost layer 6 also has unevenness. Therefore, in FIG. 4(b), for example, when the part directly below arrow A is focused and exposed, a narrow image is formed in the part directly below arrow B. Therefore, when the polycrystalline silicon layer 5 is etched after exposure and development, f
- As shown in FIG. 5, the width of the upper electrode 7 is non-uniform not only in the gate 7 but also in the device region, making it difficult to reliably control device characteristics when miniaturized. In addition, the fifth
Reference numeral 10 in the figure indicates a region of the field oxide film 2 excluding the flat portion. In addition, since the polycrystalline silicon J-5 has irregularities, the thickness of the resist is not uniform, and it is difficult to cut through the resist. For this reason, in the prior art, in order to ensure that the y-upper electrode 7 is placed on the element region 3, the gate fringe 1 is
1 will need to be made longer.

[Object of the Invention] The present invention has been made in view of the above circumstances, and it is possible to eliminate unevenness in the thickness of the Renost layer coated thereon by eliminating unevenness and flattening the f-upper electrode material layer. Motte r-
It is an object of the present invention to provide a method for manufacturing a highly integrated semiconductor device that can achieve high integration of an upper electrode.

[Summary of the invention]

The present invention can be applied directly onto the gate electrode material layer or by applying the same to the gate electrode material layer.
The main feature of this method is that immediately after the arm turning, a renost layer is formed at the same etching rate as the dirt electrode material layer to flatten the entire surface, and then etching by RIE and patterning of the gate electrode material are performed to achieve the above-mentioned purpose. This is what we are trying to achieve.

[Embodiments of the invention]

Hereinafter, a case in which the present invention is applied to manufacturing an MO8 type transistor will be described with reference to the drawings.

Embodiment 1 First, a field oxide film 22 is formed on the surface of, for example, a P-type silicon substrate 21, and then this nine field oxide film 22 is formed.
An element region 23 KP surrounded by a fi film 24 was formed. Subsequently, a polycrystalline silicon No. 25 having an etching speed of about 3000X/RF11n and a resist layer 26 having a low viscosity and the same etching speed as the polycrystalline silicon layer 25 were applied as a Y-to-G electrode material layer on the entire surface. . As a result, the entire surface was flattened (as shown in Cm1 in FIG. 1).

Subsequently, the resist layer 26 and the polycrystalline silicon layer 2
5 was etched by reactive ion etching (RIK) until the surface of the field oxide film 22 was exposed.

As a result, the surface of the etched polycrystalline silicon layer 25 became flat at the same level as the surface of the field oxide film 22 (as shown in FIG. 1 (b3)). The polycrystalline silicon layer 25 was formed on the silicon layer 25 (as shown in FIG. 1). Thereafter, the polycrystalline silicon layer 25 was selectively etched away using the resist pattern 27 as a mask, and an r-upper electrode 28 made of polycrystalline silicon was formed. Furthermore, after selectively removing the y-t oxide film 24 using this f-) electrode 28 as a mask,
r-) Using the electrode 28 as a mask, n-type impurities were introduced into the substrate 21 to form P-type source and drain regions 29 and 30 (FIG. 1 "j", shown in FIGS. 2 and 3). So, Figure 2 is the top view of the first figure (dl), and Figure 3 is the X of Figure 2.
- It is a sectional view along the X-line. In FIG. 2, reference numeral 31 indicates a region of the field oxide film 22 excluding the flat part (device region and sloped part of the field oxide film), and 32 (shaded region) indicates r-
) indicates a fringe.

According to the first embodiment, since the renost layer 26 having the same etching rate and low viscosity is formed on the polycrystalline silicon layer 25, the entire surface can be made flat without unevenness.

As a result, in the conventional technique, an image distorted from the mask pattern was formed during exposure, whereas in this embodiment, an image without distortion can be formed on the resist layer 26. Therefore, R.I.
By appropriately etching the resist layer 26 and the polycrystalline silicon layer 25 from EI7C, the polycrystalline silicon layer 25 can remain only in the region 31 at the same level as the surface of the field oxide film 22, as shown in FIG. 1b1. By selectively etching the resist pattern 27 using the resist pattern 27 as a mask, a Y-upper electrode 28 having a uniform width can be formed as shown in FIG. Therefore, the characteristics of each element in the integrated circuit can be reliably controlled.

Furthermore, as described above, by etching the polycrystalline silicon layer 25 until its surface becomes flush with the surface of the polycrystalline silicon layer 25, the gate 7 liner 32 can be formed in a self-aligned manner. f-) The length of the 7-line connector 32 can be made shorter than in the past, and the intervals between elements or the intervals between elements and wiring can be narrowed to achieve high integration.

Example 2 First, in the same manner as in Example 1, a field oxide film 22 and a gate oxide film 24 were formed on the surface of a P-type silicon substrate 21. Next, after depositing a polycrystalline silicon layer on the entire surface,
A polycrystalline silicon pattern 41 is formed by patterning. Next, a resist M42 having the same etching speed as the silicon M4 turf 41 and having a low viscosity was formed on the entire surface (see FIG. 7 (a1)).
142 and polycrystalline silicon/9 turns 41 were etched by RIE until the surface of field oxide film 22 was exposed. As a result, the surface of polycrystalline silicon pattern 41 and the surface of field oxide film 22 became on the same plane.

The following is the same as in Example 1. -) Formation of electrode 43, selective etching of gate d-oxide film 24, N+ type source,
Drain regions 29 and 30 were formed to fabricate an MO8O8 type transistor (as shown in FIG. 7 and FIG. 8). here,
FIG. 8 is a cross-sectional view taken in the width direction of the seventh δ gate W: pole.

However, according to the second embodiment, effects similar to those of the first embodiment can be obtained.

Example 3 First, in the same manner as in Example 1, a field oxide film 22 and an 'i'-to oxide film 24 were formed on the surface of a P-type silicon substrate 21, and a polycrystalline silicon layer 25 and a Renost Wt 26 were formed. (Illustrated in Figure 9 ra1).

Subsequently, the resist layer 26 and the polycrystalline silicon layer 2
5 was etched by RIE until the polycrystalline silicon layer 25 was flattened (as shown in FIG. 9(b)). Thereafter, the polycrystalline silicon layer 25t is patterned by a conventional method to form an r-upper electrode 51, and inner source and drain regions (none of which are shown) are formed to form a MOS! A transition edge was manufactured (9th crystal presentation).

Therefore, according to the third embodiment, the same effects as those of the first embodiment can be obtained.

In the above embodiment, a polycrystalline silicon layer is used as the r-upper electrode material layer, but the present invention is not limited to this. For example, M.O.
A gold FA layer, a metal silicide layer such as a MoS2 layer, etc. may also be used.

In addition, in the above embodiment, the case where it is applied to the MO8O8 type transistor structure is described, but it is not limited to this.
It can be similarly applied to yL construction such as 8-type Tranostar.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to eliminate the unevenness in the thickness of the Renost layer applied on the 'r'-top electrode material layer and to miniaturize the y-top electrode, thereby achieving highly integrated semiconductor devices. We can provide a manufacturing method.

[Brief explanation of drawings]

Figures m1 (a) to ((to) are cross-sectional views showing the manufacturing method of an MO8 type transistor according to Example 10 of the present invention in the order of steps, Figure 2 is a plan view of Figure 1 (Fig. X-X?sK
Cross-sectional view along Fig. 4 (a) to (c) c. Conventional MO8
Cross-sectional diagram showing the manufacturing method of the type Tranostar in order of steps, No. 5
The figure is a plan view of Fig. 4 rc), and Fig. 6 is a plan view of Fig. ff15.
7(d) and (b) are cross-sectional views showing the manufacturing method of the MO8 type transistor according to the second embodiment of the present invention in the order of steps, and FIG. 8 is a cross-sectional view taken along the X-ray. Cross-sectional views cut in the width direction, FIGS. ...field oxide film, 23...element region, 24...r-) oxidation l
i Ministry, 25... Polycrystalline silicon layer, 26.42...
Renost layer, 27...Resist number turns, 28.4
3゜5ノ...Dirt electrode, 29...N1 source region, 30...P type drain region, 32...r-)
Fringe, 41...polycrystalline silicon pattern. Applicant's attorney Hiko Ushiki, Patent Attorney Dosu, [No. 60, 9th cause]

Claims (2)

[Claims] (1) A step of forming an element isolation region on the surface of a semiconductor substrate, a step of forming a gate oxide film in the element region of the substrate surrounded by the element isolation region, and a step of forming a gate electrode material layer on the entire surface. a step of forming a resist layer having the same etching rate as the gate electrode material layer directly or immediately after patterning the gate electrode material layer; and reactive ion etching of the resist layer and the gate electrode material layer. 1. A method for manufacturing a semiconductor device, comprising: etching the gate electrode material layer so that it remains so as to planarize the entire surface; and patterning the gate electrode material layer to form a gate electrode. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode material layer is a polycrystalline silicon layer.